From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Dec 2021 12:30:56 +0000 (+0000)
Subject: absolute import again
X-Git-Tag: sv_maxu_works-initial~654
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f7a74eaccc787ca0f742c076d47beb6834489e7;p=openpower-isa.git

absolute import again
---

diff --git a/src/openpower/decoder/test/pysim.py b/src/openpower/decoder/test/pysim.py
index 0d70032b..531a7e83 100644
--- a/src/openpower/decoder/test/pysim.py
+++ b/src/openpower/decoder/test/pysim.py
@@ -6,7 +6,7 @@ from vcd.gtkw import GTKWSave
 from nmigen.hdl import ClockSignal, ResetSignal
 from nmigen.hdl.ast import SignalDict
 from nmigen.sim._base import BaseSignalState, BaseSimulation, BaseEngine
-from _pyrtl import _FragmentCompiler
+from openpower.decoder.test._pyrtl import _FragmentCompiler
 from nmigen.sim._pycoro import PyCoroProcess
 from nmigen.sim._pyclock import PyClockProcess