From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 May 2019 10:19:47 +0000 (+0100)
Subject: make write latch sync in Function Unit
X-Git-Tag: div_pipeline~2105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f7c934980d064c30829217e7d1af1682061c81e;p=soc.git

make write latch sync in Function Unit
---

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 32571b90..5cc54540 100644
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -141,11 +141,11 @@ class Scoreboard(Elaboratable):
             fn_issue_l.append(fu.issue_i)
             fn_busy_l.append(fu.busy_o)
             # XXX sync, so as to stop a simulation infinite loop
-            m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
-            m.d.sync += fu.dest_i.eq(issueunit.i.dest_i)
-            m.d.sync += fu.src1_i.eq(issueunit.i.src1_i)
-            m.d.sync += fu.src2_i.eq(issueunit.i.src2_i)
-            m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o)
+            m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
+            m.d.comb += fu.dest_i.eq(issueunit.i.dest_i)
+            m.d.comb += fu.src1_i.eq(issueunit.i.src1_i)
+            m.d.comb += fu.src2_i.eq(issueunit.i.src2_i)
+            m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
 
         #---------
         # connect Function Units
diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index a21911d3..ba4e1929 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -79,7 +79,7 @@ class FnUnit(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         m.submodules.rd_l = rd_l = SRLatch(sync=False)
-        m.submodules.wr_l = wr_l = SRLatch(sync=False)
+        m.submodules.wr_l = wr_l = SRLatch(sync=True)
         m.submodules.dest_d = dest_d = Decoder(self.reg_width)
         m.submodules.src1_d = src1_d = Decoder(self.reg_width)
         m.submodules.src2_d = src2_d = Decoder(self.reg_width)
diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index a5d4db1b..f8ab4015 100644
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -11,7 +11,7 @@ class GlobalPending(Elaboratable):
         Pending.  Can be used for INT or FP Global Pending.
 
         Inputs:
-        * :wid:       register file width
+        * :dep:       register file depth
         * :fu_vecs:   a python list of function unit "pending" vectors, each
                       vector being a Signal of width equal to the reg file.
 
@@ -26,12 +26,12 @@ class GlobalPending(Elaboratable):
           on a particular register (extremely unusual), they must set a Const
           zero bit in the vector.
     """
-    def __init__(self, wid, fu_vecs):
-        self.reg_width = wid
+    def __init__(self, dep, fu_vecs):
+        self.reg_dep = dep
         # inputs
         self.fu_vecs = fu_vecs
         for v in fu_vecs:
-            assert len(v) == wid, "FU Vector must be same width as regfile"
+            assert len(v) == dep, "FU Vector must be same width as regfile"
 
         self.g_pend_o = Signal(wid, reset_less=True)  # global pending vector