From: lkcl <lkcl@web>
Date: Sun, 25 Sep 2022 00:05:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~301
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f863b0e2a872e4682a82854de96c53bd7f97eb9;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index 9424dd5ca..525f8c22d 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -223,7 +223,8 @@ also define Registers:
      RA = B0 || B1 || B2 || B3 || B4 || B5 || B6 || B7
 
 Further we may now also define half-words, words, and double-words,
-confirming the definition of registers (RA as the same example):
+confirming the definition of registers, RA as the same example, above,
+where all definitions of RA below are consistent / identical:
 
      H0 = B0||B1, H1 = B2||B3, H2 = B4||B5, H3 = B6||B7
      RA = H0||H1||H2||H3
@@ -262,3 +263,17 @@ same results as above:
     y.l[0] = 128;
     z.l[0] = 3 + 4;
 
+Next, elements are introduced.  Using the definition `int_regfile` above
+let us perform two operations:
+
+    int_regfile[2].s[1] = 1<<3
+    int_regfile[2].s[4] = 1<<9
+    RA = GPR(2)
+    RB = GPR(3)
+
+Examining the contents of RA is found to be:
+
+    RA.H0 = 0x0000  RA.H1 = 0x0000  RA.H2 = 0x0008   RA.H3 = 0x0000
+    RB.H0 = 0x0000  RB.H1 = 0x0000  RB.H2 = 0x0008   RB.H3 = 0x0100
+
+The reason