From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 15:37:27 +0000 (-0700)
Subject: Respect opt_expr -keepdc as per @cliffordwolf
X-Git-Tag: working-ls180~1111^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f971470f83b8e4ed29232be4b6cb5da89d50dc0;p=yosys.git

Respect opt_expr -keepdc as per @cliffordwolf
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c4da613ab..73f48317a 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -748,7 +748,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in(ID($shiftx), ID($shift))) {
 			SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			int width;
-			bool trim_x = true;
+			bool trim_x = cell->type == ID($shiftx) || !keepdc;
 			bool trim_0 = cell->type == ID($shift);
 			for (width = GetSize(sig_a); width > 1; width--) {
 				if ((trim_x && sig_a[width-1] == State::Sx) ||
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 02be20a62..ecc2c8da8 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -277,3 +277,17 @@ check
 equiv_opt opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
+    \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -keepdc
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=13 %i