From: Lukasz Dalek Date: Mon, 1 Jun 2020 13:25:24 +0000 (+0200) Subject: Parse macro call attached semicolon as empty expression X-Git-Tag: working-ls180~431^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f9be93;p=yosys.git Parse macro call attached semicolon as empty expression Signed-off-by: Lukasz Dalek --- diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 18745e38e..35e34a124 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -745,7 +745,7 @@ module_body: module_body_stmt: task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | enum_decl | struct_decl | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';'; checker_decl: TOK_CHECKER TOK_ID ';' {