From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 29 Jun 2020 12:37:02 +0000 (+0200)
Subject: Fix PLL instanciation code for CRG simulation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6f9e8c2668130a49577236e3b338e6a9ec8ed7ee;p=gram.git

Fix PLL instanciation code for CRG simulation
---

diff --git a/gram/simulation/simcrg.py b/gram/simulation/simcrg.py
index 12b713a..dd07615 100644
--- a/gram/simulation/simcrg.py
+++ b/gram/simulation/simcrg.py
@@ -32,9 +32,6 @@ class PLL(Elaboratable):
     def elaborate(self, platform):
         clkfb = Signal()
         pll = Instance("EHXPLLL",
-                       p_PLLRST_ENA='DISABLED',
-                       p_INTFB_WAKE='DISABLED',
-                       p_STDBY_ENABLE='DISABLED',
                        p_CLKOP_FPHASE=0,
                        p_CLKOP_CPHASE=1,
                        p_OUTDIVIDER_MUXA='DIVA',
@@ -45,19 +42,19 @@ class PLL(Elaboratable):
                        p_CLKOS3_DIV=self.CLKOS3_DIV,
                        p_CLKFB_DIV=self.CLKFB_DIV,
                        p_CLKI_DIV=self.CLKI_DIV,
-                       p_FEEDBK_PATH='CLKOP',
+                       p_FEEDBK_PATH='INT_OP',
                        #p_FREQUENCY_PIN_CLKOP='200',
                        i_CLKI=self.clkin,
                        i_CLKFB=clkfb,
                        i_RST=0,
                        i_STDBY=0,
-                       i_PHASESEL0=0,
-                       i_PHASESEL1=0,
+                       i_PHASESEL0=1,
+                       i_PHASESEL1=1,
                        i_PHASEDIR=0,
                        i_PHASESTEP=0,
                        i_PLLWAKESYNC=0,
-                       i_ENCLKOP=0,
-                       i_ENCLKOS=0,
+                       i_ENCLKOP=1,
+                       i_ENCLKOS=1,
                        i_ENCLKOS2=0,
                        i_ENCLKOS3=0,
                        o_CLKOP=self.clkout1,