From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 6 Mar 2013 10:30:52 +0000 (+0100)
Subject: fhdl/verilog: tristate outputs are always wire
X-Git-Tag: 24jan2021_ls180~2099^2~676
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fa30053bf1b247007426e61bee1a286f0226390;p=litex.git

fhdl/verilog: tristate outputs are always wire
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index bc0a19c4..c5ba2272 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -135,10 +135,10 @@ def _list_comb_wires(f):
 
 def _printheader(f, ios, name, ns):
 	sigs = list_signals(f) | list_special_ios(f, True, True, True)
-	it_mem_outs = list_special_ios(f, False, True, False)
+	special_outs = list_special_ios(f, False, True, True)
 	inouts = list_special_ios(f, False, False, True)
-	targets = list_targets(f) | it_mem_outs
-	wires = _list_comb_wires(f) | it_mem_outs
+	targets = list_targets(f) | special_outs
+	wires = _list_comb_wires(f) | special_outs
 	r = "module " + name + "(\n"
 	firstp = True
 	for sig in sorted(ios, key=lambda x: x.huid):