From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 12 Feb 2019 17:21:46 +0000 (-0800)
Subject: Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
X-Git-Tag: yosys-0.9~232^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6faad18874d38ee2987d9cec573b5b3c8a41f279;p=yosys.git

Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aiger
---

6faad18874d38ee2987d9cec573b5b3c8a41f279
diff --cc frontends/aiger/aigerparse.cc
index 888a4afe6,1e13e1124..7df28fe87
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -234,9 -235,12 +233,8 @@@ void AigerReader::parse_aiger_ascii(
          RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
          RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
          RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 -
 -        RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
 -        and_cell->setPort("\\A", i1_wire);
 -        and_cell->setPort("\\B", i2_wire);
 -        and_cell->setPort("\\Y", o_wire);
 +        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
      }
-     std::getline(f, line); // Ignore up to start of next line
  }
  
  static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)