From: Sandra Loosemore Date: Thu, 26 Feb 2015 21:55:37 +0000 (-0500) Subject: extend.texi (Function Attributes): Fix spelling and typos. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fb04b89fbfc2d48c637562504994a5d32cf8854;p=gcc.git extend.texi (Function Attributes): Fix spelling and typos. 2015-02-26 Sandra Loosemore gcc/ * doc/extend.texi (Function Attributes): Fix spelling and typos. (Label Attributes): Likewise. (Cilk Plus Builtins): Likewise. (ARC SIMD Built-in Functions): Likewise. (ARM C Language Extensions (ACLE)): Likewise. (PowerPC Built-in Functions): Likewise. (PowerPC Hardware Transactional Memory Built-in Functions): Likewise. From-SVN: r221035 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 97434356dac..e0bafa794e4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-02-26 Sandra Loosemore + + * doc/extend.texi (Function Attributes): Fix spelling and typos. + (Label Attributes): Likewise. + (Cilk Plus Builtins): Likewise. + (ARC SIMD Built-in Functions): Likewise. + (ARM C Language Extensions (ACLE)): Likewise. + (PowerPC Built-in Functions): Likewise. + (PowerPC Hardware Transactional Memory Built-in Functions): + Likewise. + 2015-02-26 Jakub Jelinek PR tree-optimization/65216 diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 54c1941ccf0..c066d32274e 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2985,7 +2985,7 @@ which this handler should be assigned. If the argument is a name it is treated as a symbolic name for the vector slot. These names should match up with appropriate entries in the linker script. By default the names @code{watchdog} for vector 26, @code{nmi} for vector 30 and -@code{reset} for vector 31 are recognised. +@code{reset} for vector 31 are recognized. You can also use the following function attributes to modify how normal functions interact with interrupt functions: @@ -3388,7 +3388,7 @@ the function label. A second argument can be used to specify the number of halfwords to be added after the function label. For both arguments the maximum allowed value is 1000000. -If both ar guments are zero, hotpatching is disabled. +If both arguments are zero, hotpatching is disabled. @item naked @cindex function without a prologue/epilogue code @@ -4633,7 +4633,7 @@ This example uses the @code{cold} label attribute to indicate the asm goto ("some asm" : : : : NoError); -/* This branch (the fallthru from the asm) is less commonly used */ +/* This branch (the fall-through from the asm) is less commonly used */ ErrorHandling: __attribute__((cold, unused)); /* Semi-colon is required here */ printf("error\n"); @@ -8988,7 +8988,7 @@ returns -1. @node Cilk Plus Builtins @section Cilk Plus C/C++ Language Extension Built-in Functions -GCC provides support for the following built-in reduction funtions if Cilk Plus +GCC provides support for the following built-in reduction functions if Cilk Plus is enabled. Cilk Plus can be enabled using the @option{-fcilkplus} flag. @itemize @bullet @@ -10744,7 +10744,7 @@ __v8hi __builtin_arc_vupsbaw (__v8hi) __v8hi __builtin_arc_vupsbw (__v8hi) @end example -The followign take two @code{int} arguments and return no result: +The following take two @code{int} arguments and return no result: @example void __builtin_arc_vdirun (int, int) void __builtin_arc_vdorun (int, int) @@ -10983,11 +10983,11 @@ intrinsics can be found at The built-in intrinsics for the Advanced SIMD extension are available when NEON is enabled. -Currently, ARM and AArch64 back-ends do not support ACLE 2.0 fully. Both -back-ends support CRC32 intrinsics from @file{arm_acle.h}. The ARM backend's -16-bit floating-point Advanded SIMD Intrinsics currently comply to ACLE v1.1. -AArch64's backend does not have support for 16-bit floating point Advanced SIMD -Intrinsics yet. +Currently, ARM and AArch64 back ends do not support ACLE 2.0 fully. Both +back ends support CRC32 intrinsics from @file{arm_acle.h}. The ARM back end's +16-bit floating-point Advanced SIMD intrinsics currently comply to ACLE v1.1. +AArch64's back end does not have support for 16-bit floating point Advanced SIMD +intrinsics yet. See @ref{ARM Options} and @ref{AArch64 Options} for more information on the availability of extensions. @@ -12451,7 +12451,7 @@ unsigned int addg6s (unsigned int, unsigned int); @end smallexample The @code{__builtin_divde}, @code{__builtin_divdeo}, -@code{__builitin_divdeu}, @code{__builtin_divdeou} functions require a +@code{__builtin_divdeu}, @code{__builtin_divdeou} functions require a 64-bit environment support ISA 2.06 or later. The following built-in functions are available for the PowerPC family @@ -12467,9 +12467,9 @@ _Decimal128 __builtin_denbcdq (int, _Decimal128); _Decimal64 __builtin_diex (_Decimal64, _Decimal64); _Decimal128 _builtin_diexq (_Decimal128, _Decimal128); _Decimal64 __builtin_dscli (_Decimal64, int); -_Decimal128 __builitn_dscliq (_Decimal128, int); +_Decimal128 __builtin_dscliq (_Decimal128, int); _Decimal64 __builtin_dscri (_Decimal64, int); -_Decimal128 __builitn_dscriq (_Decimal128, int); +_Decimal128 __builtin_dscriq (_Decimal128, int); unsigned long long __builtin_unpack_dec128 (_Decimal128, int); _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); @end smallexample @@ -15079,7 +15079,7 @@ must be a constant integer in the range of 0 to 15. @subsection PowerPC Hardware Transactional Memory Built-in Functions GCC provides two interfaces for accessing the Hardware Transactional Memory (HTM) instructions available on some of the PowerPC family -of prcoessors (eg, POWER8). The two interfaces come in a low level +of processors (eg, POWER8). The two interfaces come in a low level interface, consisting of built-in functions specific to PowerPC and a higher level interface consisting of inline functions that are common between PowerPC and S/390. @@ -19255,4 +19255,4 @@ than no arguments, as C++ demands. @end table @c LocalWords: emph deftypefn builtin ARCv2EM SIMD builtins msimd -@c LocalWords: typedef v4si v8hi DMA dma vdiwr vdowr followign +@c LocalWords: typedef v4si v8hi DMA dma vdiwr vdowr