From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 1 Dec 2023 07:27:48 +0000 (-0800)
Subject: caller.py: implement exit_group syscall
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fca84f17c4962398f55ddc113ad3ccdb878655d;p=openpower-isa.git

caller.py: implement exit_group syscall
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index ee26d153..61a0b35b 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1148,6 +1148,10 @@ class StepLoop:
         log("    new dststep", dststep)
 
 
+class ExitSyscallCalled(Exception):
+    pass
+
+
 class SyscallEmulator(openpower.syscalls.Dispatcher):
     def __init__(self, isacaller):
         self.__isacaller = isacaller
@@ -1162,6 +1166,10 @@ class SyscallEmulator(openpower.syscalls.Dispatcher):
         (identifier, *arguments) = map(int, (identifier, *arguments))
         return super().__call__(identifier, *arguments)
 
+    def sys_exit_group(self, status, *rest):
+        self.__isacaller.halted = True
+        raise ExitSyscallCalled(status)
+
 
 class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
     # decoder2 - an instance of power_decoder2
diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index ea6edb6f..47010a44 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -28,6 +28,7 @@ from nmutil.sim_tmp_alternative import Simulator, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmutil.gtkw import write_gtkw
 from openpower.decoder.isa.all import ISA
+from openpower.decoder.isa.caller import ExitSyscallCalled
 from openpower.endian import bigendian
 
 from openpower.decoder.power_decoder2 import PowerDecode2
@@ -107,7 +108,10 @@ class SimRunner(StateRunner):
 
             # call simulated operation
             log("sim", code)
-            yield from sim.execute_one()
+            try:
+                yield from sim.execute_one()
+            except ExitSyscallCalled:
+                break
             yield Settle()
             index = sim.pc.CIA.value//4
 
@@ -274,7 +278,10 @@ class TestRunnerBase(FHDLTestCase):
                     log("sprs", test.sprs, kind=LogType.InstrInOuts)
                     log("cr", test.cr, kind=LogType.InstrInOuts)
                     log("mem", test.mem)
-                    log("msr", test.msr, kind=LogType.InstrInOuts)
+                    if test.msr is None:
+                        log("msr", "None", kind=LogType.InstrInOuts)
+                    else:
+                        log("msr", hex(test.msr), kind=LogType.InstrInOuts)
 
                     def format_assembly(assembly):
                         # type: (str) -> str