From: lkcl <lkcl@web>
Date: Sat, 30 Apr 2022 17:54:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2532
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fce731150c6e6c9bbff15aa62e15675907a7bc7;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 37bfcd006..4d7b7b46a 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -1068,13 +1068,13 @@ that is offset by MAXVL, both halves actually starting from RT.
 If VL is 3, MAXVL is 5, RT is 1, and dest elwidth is 32 then the elements
 RT0 to RT2 are stored:
 
-         0..31     32..63
+          0..31     32..63
      r0  unchanged unchanged
      r1  RT0.lo    RT1.lo
      r2  RT2.lo    unchanged
      r3  unchanged RT0.hi
      r4  RT1.hi    RT2.hi
-     r5 unchanged  unchanged
+     r5  unchanged unchanged
 
 Additional DRAFT Scalar instructions in 3-in 2-out form
 with an implicit 2nd destination: