From: lkcl <lkcl@web>
Date: Mon, 1 Jul 2019 08:09:46 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4311
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fcf44336972904be3a9d2f70e8e7c8c7320a441;p=libreriscv.git

---

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 359d3e454..d7f98720c 100644
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -118,7 +118,7 @@ It leaves space for future expansion to RV128 and/or multi-register predicates.
 
 GETVL add1 SETVL is a pain. 3 operations because VL is a CSR it is not possible to perform arithmetic on it.
 
-What about actually marking one of the registers *as* VL?
+What about actually marking one of the registers *as* VL?  this would save a *lot* of instructions.
 
 ----
 
@@ -127,3 +127,4 @@ Setting VL from an immed without altering MVL is not possible in the above pseud
 # links
 
 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-June/001881.html>
+* <https://groups.google.com/d/msg/comp.arch/MLfqE8Rm-X4/zHLCHg6UAQAJ>