From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 11:11:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1724
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fdb5983ff242ab19399ebd664bdabe12c39ad50;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 1039abb59..77dab8ef7 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -6,7 +6,7 @@ Obligatory Dilbert:
 
 ===
 
-# SV (Simple Vectorisation) for the Power ISA
+# SV (Simple Scalar Vectorisation) for the Power ISA
 
 **SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review.
 
@@ -28,13 +28,14 @@ Fundamental design principles:
   for-loop had been expanded as actual scalar instructions
   (termed "preserving Program Order")
 * Augments ("tags") existing instructions, providing Vectorisation
-  "context" rather than adding new ones.
+  "context" rather than adding new instructions.
 * Does not modify or deviate from the underlying scalar Power ISA
   unless it provides significant performance or other advantage to do so
-  in the Vector space (dropping XER.SO for example)
+  in the Vector space (dropping "sticky" of XER.SO for example)
 * Designed for Supercomputing: avoids creating significant sequential
-  dependency hazards, allowing high performance superscalar
-  microarchitectures to be deployed.
+  dependency hazards, allowing standard
+  high performance superscalar multi-issue
+  micro-architectures to be leveraged.
 
 Advantages of these design principles: