From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 Jul 2020 11:59:13 +0000 (+0100)
Subject: add TT.size and use it in PowerDecoder and trap input record
X-Git-Tag: semi_working_ecp5~631
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fdd20058913fbf02ca607001da56e07d5486fd0;p=soc.git

add TT.size and use it in PowerDecoder and trap input record
---

diff --git a/src/soc/consts.py b/src/soc/consts.py
index ee5b4bae..27d5b37d 100644
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -50,3 +50,5 @@ class TT:
     TRAP = 1<<2
     ADDR = 1<<3
     ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits
+    # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
+    size = 5 # MUST update this to contain the full number of Trap Types
diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index 410cb7ec..c5c20945 100644
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -6,6 +6,7 @@ based on Anton Blanchard microwatt decode2.vhdl
 from nmigen import Signal, Record
 from nmutil.iocontrol import RecordObject
 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
+from soc.consts import TT
 
 
 class Data(Record):
@@ -54,7 +55,7 @@ class Decode2ToOperand(RecordObject):
         self.byte_reverse  = Signal(reset_less=True)
         self.sign_extend  = Signal(reset_less=True)# do we need this?
         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
-        self.traptype  = Signal(5, reset_less=True) # see trap main_stage.py
+        self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
         self.trapaddr  = Signal(13, reset_less=True)
         self.read_cr_whole = Signal(reset_less=True)
         self.write_cr_whole = Signal(reset_less=True)
diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index f7613790..dd87f30f 100644
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,5 +1,6 @@
 from soc.fu.base_input_record import CompOpSubsetBase
 from soc.decoder.power_enums import (MicrOp, Function)
+from soc.consts import TT
 
 
 class CompTrapOpSubset(CompOpSubsetBase):
@@ -16,7 +17,7 @@ class CompTrapOpSubset(CompOpSubsetBase):
                   ('msr', 64), # TODO: "state" in separate Record
                   ('cia', 64), # likewise
                   ('is_32bit', 1),
-                  ('traptype', 5), # see trap main_stage.py and PowerDecoder2
+                  ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),
                   )