From: Eric Anholt <eric@anholt.net>
Date: Thu, 20 Jun 2013 23:10:43 +0000 (-0700)
Subject: i965: Drop code checking for gen <= 3.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fddd375d79e9f94668dace0d50f571654792222;p=mesa.git

i965: Drop code checking for gen <= 3.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 8c6524e71af..a5386910e22 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -543,7 +543,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
 	 OUT_BATCH(0); /* write data */
 	 ADVANCE_BATCH();
       }
-   } else if (intel->gen >= 4) {
+   } else {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
 		PIPE_CONTROL_WRITE_FLUSH |
@@ -552,9 +552,5 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
       OUT_BATCH(0); /* write data */
       OUT_BATCH(0); /* write data */
       ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(1);
-      OUT_BATCH(MI_FLUSH);
-      ADVANCE_BATCH();
    }
 }
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 23d8281b4ca..2a325cd8438 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -363,9 +363,6 @@ intel_flush_rendering_to_batch(struct gl_context *ctx)
 
    if (intel->Fallback)
       _swrast_flush(ctx);
-
-   if (intel->gen < 4)
-      INTEL_FIREVERTICES(intel);
 }
 
 void
@@ -552,11 +549,8 @@ intelInitContext(struct intel_context *intel,
 	  0, sizeof(ctx->TextureFormatSupported));
 
    driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
-                       sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
-   if (intel->gen < 4)
-      intel->maxBatchSize = 4096;
-   else
-      intel->maxBatchSize = BATCH_SZ;
+                       sPriv->myNum, "i965");
+   intel->maxBatchSize = BATCH_SZ;
 
    /* Estimate the size of the mappable aperture into the GTT.  There's an
     * ioctl to get the whole GTT size, but not one to get the mappable subset.
@@ -564,8 +558,6 @@ intelInitContext(struct intel_context *intel,
     * was smaller.
     */
    uint32_t gtt_size = 256 * 1024 * 1024;
-   if (intel->gen == 2)
-      gtt_size = 128 * 1024 * 1024;
 
    /* We don't want to map two objects such that a memcpy between them would
     * just fault one mapping in and then the other over and over forever.  So
@@ -608,11 +600,7 @@ intelInitContext(struct intel_context *intel,
     */
    _mesa_init_point(ctx);
 
-   if (intel->gen >= 4) {
-      ctx->Const.MaxRenderbufferSize = 8192;
-   } else {
-      ctx->Const.MaxRenderbufferSize = 2048;
-   }
+   ctx->Const.MaxRenderbufferSize = 8192;
 
    /* Initialize the software rasterizer and helper modules.
     *
@@ -620,7 +608,7 @@ intelInitContext(struct intel_context *intel,
     * software fallbacks (which we have to support on legacy GL to do weird
     * glDrawPixels(), glBitmap(), and other functions).
     */
-   if (intel->gen <= 3 || api != API_OPENGL_CORE) {
+   if (api != API_OPENGL_CORE) {
       _swrast_CreateContext(ctx);
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 058cfbe1bcc..4cc2e5bc561 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -473,9 +473,8 @@ intel_miptree_choose_tiling(struct intel_context *intel,
    }
 
    GLenum base_format = _mesa_get_format_base_format(format);
-   if (intel->gen >= 4 &&
-       (base_format == GL_DEPTH_COMPONENT ||
-        base_format == GL_DEPTH_STENCIL_EXT))
+   if (base_format == GL_DEPTH_COMPONENT ||
+       base_format == GL_DEPTH_STENCIL_EXT)
       return I915_TILING_Y;
 
    int minimum_pitch = mt->total_width * mt->cpp;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 60a69a60648..34e0caa81ca 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -167,9 +167,6 @@ intelDRI2Flush(__DRIdrawable *drawable)
    if (intel == NULL)
       return;
 
-   if (intel->gen < 4)
-      INTEL_FIREVERTICES(intel);
-
    intel_resolve_for_dri2_flush(intel, drawable);
    intel->need_throttle = true;
 
@@ -836,13 +833,8 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
    else if (mesaVis->alphaBits == 0)
       rgbFormat = MESA_FORMAT_XRGB8888;
    else {
-      if (screen->gen >= 4) {
-         rgbFormat = MESA_FORMAT_SARGB8;
-         fb->Visual.sRGBCapable = true;
-      } else {
-         rgbFormat = MESA_FORMAT_ARGB8888;
-      }
-
+      rgbFormat = MESA_FORMAT_SARGB8;
+      fb->Visual.sRGBCapable = true;
    }
 
    /* setup the hardware-based renderbuffers */
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index b91b2b5dccb..b359c57145a 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -85,7 +85,7 @@ intel_miptree_create_for_teximage(struct intel_context *intel,
       if ((intelObj->base.Sampler.MinFilter == GL_NEAREST ||
 	   intelObj->base.Sampler.MinFilter == GL_LINEAR) &&
 	  intelImage->base.Base.Level == firstLevel &&
-	  (intel->gen < 4 || firstLevel == 0)) {
+	  firstLevel == 0) {
 	 lastLevel = firstLevel;
       } else {
 	 lastLevel = (firstLevel +