From: yimmanuel3@f4ac60d763911c3fa518755176e4b9ed455c75d8 <yimmanuel3@web>
Date: Sun, 2 Feb 2020 08:43:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3625
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fded74e52e48bac91448bd7541dd66672bc09eb;p=libreriscv.git

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diff --git a/index.mdwn b/index.mdwn
index 5af89167e..208062bac 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -1,4 +1,5 @@
 # Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
+## Why a Libre SOC?
 
 Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com):
 
@@ -8,10 +9,15 @@ Given the fact that [high performing]bug free processors don’t exist anymore,
 
 Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve intelligence, media consumption, wireless connectivity, etc.
 
+## What we Do
 LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to  study, modify, and redistribute the processor source from HDL to VLSI.
 
 Right now, we're targeting an (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
 
+## Still Got Questions?
+Read about the business and practical benefits of a LibreSOC below.
+[[why_a_libresoc]]
+
 # Wiki Structure
 
 This is a publicly editable wiki.
@@ -24,11 +30,6 @@ This is the sitemap: [[sitemap]]
 
 ----
 
-# Why a Libre SOC?
-Glad you asked! Read about the business and practical benefits of a LibreSOC below.
-
-[[why_a_libresoc]]
-
 # Contact
 
 The main contact point is the