From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Jul 2020 13:45:09 +0000 (+0100)
Subject: increase range of test values for extswsli
X-Git-Tag: div_pipeline~61
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fe174d9e78e3181e76d369d9988fd4a3577120c;p=soc.git

increase range of test values for extswsli
---

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index f19ba4d3..ec35aaae 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -153,7 +153,7 @@ class ShiftRotTestCase(FHDLTestCase):
             sh = random.randint(0, 63)
             lst = [f"extswsli 3, 1, {sh}"]
             initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<15)-1)
+            initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlc(self):