From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 24 Oct 2015 17:09:45 +0000 (+0200)
Subject: equiv_purge bugfix, using SigChunk in Yosys namespace
X-Git-Tag: yosys-0.6~92
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fe48cf41ef0b0158879add600c7a426a5c4a762;p=yosys.git

equiv_purge bugfix, using SigChunk in Yosys namespace
---

diff --git a/kernel/yosys.h b/kernel/yosys.h
index 6aacd4d54..af849fca8 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -169,6 +169,7 @@ namespace RTLIL {
 	struct IdString;
 	struct Const;
 	struct SigBit;
+	struct SigChunk;
 	struct SigSpec;
 	struct Wire;
 	struct Cell;
@@ -184,6 +185,7 @@ namespace AST {
 using RTLIL::IdString;
 using RTLIL::Const;
 using RTLIL::SigBit;
+using RTLIL::SigChunk;
 using RTLIL::SigSpec;
 using RTLIL::Wire;
 using RTLIL::Cell;
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 34318dec2..982176c44 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -156,7 +156,7 @@ struct EquivMiterWorker
 		struct RewriteSigSpecWorker {
 			RTLIL::Module * mod;
 			void operator()(SigSpec &sig) {
-				vector<RTLIL::SigChunk> chunks = sig.chunks();
+				vector<SigChunk> chunks = sig.chunks();
 				for (auto &c : chunks)
 					if (c.wire != NULL)
 						c.wire = mod->wires_.at(c.wire->name);
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index e14ffe31c..f4141ad4d 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -162,8 +162,9 @@ struct EquivPurgeWorker
 
 		srcsig.sort_and_unify();
 
-		for (SigSpec sig : srcsig.chunks())
-			rewrite_sigmap.add(sig, make_input(sig));
+		for (SigChunk chunk : srcsig.chunks())
+			if (chunk.wire != nullptr)
+				rewrite_sigmap.add(chunk, make_input(chunk));
 
 		for (auto cell : module->cells())
 			if (cell->type == "$equiv")
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 68a7fc1f6..d9ec4bc6a 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -737,7 +737,7 @@ struct ExtractPass : public Pass {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections()) {
-						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
+						std::vector<SigChunk> chunks = sigmap(conn.second);
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires_.at(chunk.wire->name);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 592710eda..19b2bda9c 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -49,7 +49,7 @@ void apply_prefix(std::string prefix, std::string &id)
 
 void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 {
-	std::vector<RTLIL::SigChunk> chunks = sig;
+	vector<SigChunk> chunks = sig;
 	for (auto &chunk : chunks)
 		if (chunk.wire != NULL) {
 			std::string wire_name = chunk.wire->name.str();