From: Florent Kermarrec Date: Tue, 30 Jun 2020 16:32:11 +0000 (+0200) Subject: targets: add identifier on all targets and update Versa ECP5. X-Git-Tag: 24jan2021_ls180~125 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fe4994f662777554737dcd4e958cc6d51390bce;p=litex.git targets: add identifier on all targets and update Versa ECP5. --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 9b4b783b..01b9df6b 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -75,7 +75,10 @@ class BaseSoC(SoCCore): if toolchain == "symbiflow": sys_clk_freq=int(60e6) - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Arty A7", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain) diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 4cfb845d..b284e2a4 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -50,7 +50,10 @@ class BaseSoC(SoCCore): platform = de0nano.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on DE0-Nano", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -77,7 +80,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano") + parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 5f96101c..3669783e 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -47,7 +47,10 @@ class BaseSoC(SoCCore): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Genesys2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py index 5563a7e4..c3d53711 100755 --- a/litex/boards/targets/icebreaker.py +++ b/litex/boards/targets/icebreaker.py @@ -80,7 +80,10 @@ class BaseSoC(SoCCore): kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on iCEBreaker", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index e40492a7..493fc23c 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on KC705", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 79755cde..9ce42dc6 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -56,7 +56,10 @@ class BaseSoC(SoCCore): platform = kcu105.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on KCU105", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index a14ab5e5..051cb6af 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -49,7 +49,10 @@ class BaseSoC(SoCCore): platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on MiniSpartan6", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 335d447f..25273f44 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -52,7 +52,10 @@ class BaseSoC(SoCCore): platform = netv2.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on NeTV2", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index fb0224fb..3e7365ed 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -53,7 +53,10 @@ class BaseSoC(SoCCore): platform = nexys4ddr.Platform() # SoCCore ----------------------------------_----------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Nexys4DDR", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 7312ba23..f1e1f274 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -53,7 +53,10 @@ class BaseSoC(SoCCore): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Nexys Video", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 0cc31be4..3cfe4957 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -24,7 +24,10 @@ class BaseSoC(SoCCore): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX Simple SoC", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) @@ -47,7 +50,7 @@ def main(): soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("platform", help="Module name of the platform to build for") - parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build") + parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index ac490450..8608aa2b 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -74,7 +74,10 @@ class BaseSoC(SoCCore): platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on ULX3S", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index aacbf5c2..7a437bb7 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -37,7 +37,8 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() + self.reset = Signal() # Clk / Rst clk100 = platform.request("clk100") @@ -46,7 +47,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk100) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -64,20 +65,28 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) + AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs): - platform = versa_ecp5.Platform(toolchain=toolchain) + def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, toolchain="trellis", **kwargs): + platform = versa_ecp5.Platform(toolchain=toolchain, device=device) + + # FIXME: adapt integrated rom size for Microwatt + if kwargs.get("cpu_type", None) == "microwatt": + kwargs["integrated_rom_size"] = 0xb000 if with_ethernet else 0x9000 # SoCCore -----------------------------------------_---------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Versa ECP5", + ident_version = True, + **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -89,6 +98,7 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K64M16(sys_clk_freq, "1:2"), @@ -123,11 +133,16 @@ def main(): builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), + device = args.device, + with_ethernet = args.with_ethernet, + toolchain = args.toolchain, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build)