From: Andrew Waterman Date: Thu, 13 Sep 2018 06:56:49 +0000 (-0700) Subject: Update README X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6fecdb16d72b71734b35f494023f5edc8804327c;p=riscv-isa-sim.git Update README --- diff --git a/README.md b/README.md index 60c0922..018c7d3 100644 --- a/README.md +++ b/README.md @@ -1,18 +1,15 @@ -RISC-V ISA Simulator -====================== - -Author : Andrew Waterman, Yunsup Lee - -Date : June 19, 2011 - -Version : (under version control) +Spike RISC-V ISA Simulator +============================ About ------------- -The RISC-V ISA Simulator implements a functional model of one or more +Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V processors. +Spike is named after the golden spike used to celebrate the completion of the +US transcontinental railway. + Build Steps ---------------