From: Alexander Ivchenko Date: Wed, 15 Oct 2014 11:04:03 +0000 (+0000) Subject: AVX-512. 56/n. Add plus/minus/abs/neg/andnot insn. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=700e2919eb5526fc9ccbc41b4ba58a668c45a2c8;p=gcc.git AVX-512. 56/n. Add plus/minus/abs/neg/andnot insn. gcc/ * config/i386/sse.md (define_mode_iterator VI_AVX2): Extend to support AVX-512BW. (define_mode_iterator VI124_AVX2_48_AVX512F): Remove. (define_expand "3"): Remove masking support. (define_insn "*3"): Ditto. (define_expand "3_mask"): New. (define_expand "3_mask"): Ditto. (define_insn "*3_mask"): Ditto. (define_insn "*3_mask"): Ditto. (define_expand "_andnot3"): Remove masking support. (define_insn "*andnot3"): Ditto. (define_expand "_andnot3_mask"): New. (define_expand "_andnot3_mask"): Ditto. (define_insn "*andnot3"): Ditto. (define_insn "*andnot3"): Ditto. (define_insn "*abs2"): Remove masking support. (define_insn "abs2_mask"): New. (define_insn "abs2_mask"): Ditto. (define_expand "abs2"): Use VI_AVX2 mode iterator. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r216255 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 283c0d302cd..efbbe411fd7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,32 @@ +2014-10-15 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (define_mode_iterator VI_AVX2): Extend + to support AVX-512BW. + (define_mode_iterator VI124_AVX2_48_AVX512F): Remove. + (define_expand "3"): Remove masking support. + (define_insn "*3"): Ditto. + (define_expand "3_mask"): New. + (define_expand "3_mask"): Ditto. + (define_insn "*3_mask"): Ditto. + (define_insn "*3_mask"): Ditto. + (define_expand "_andnot3"): Remove masking support. + (define_insn "*andnot3"): Ditto. + (define_expand "_andnot3_mask"): New. + (define_expand "_andnot3_mask"): Ditto. + (define_insn "*andnot3"): Ditto. + (define_insn "*andnot3"): Ditto. + (define_insn "*abs2"): Remove masking support. + (define_insn "abs2_mask"): New. + (define_insn "abs2_mask"): Ditto. + (define_expand "abs2"): Use VI_AVX2 mode iterator. + 2014-10-15 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 018702afca8..a6cf3639576 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -271,8 +271,8 @@ (V4DI "TARGET_AVX") V2DI]) (define_mode_iterator VI_AVX2 - [(V32QI "TARGET_AVX2") V16QI - (V16HI "TARGET_AVX2") V8HI + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) @@ -362,12 +362,6 @@ [(V16HI "TARGET_AVX2") V8HI (V8SI "TARGET_AVX2") V4SI]) -(define_mode_iterator VI124_AVX2_48_AVX512F - [(V32QI "TARGET_AVX2") V16QI - (V16HI "TARGET_AVX2") V8HI - (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI - (V8DI "TARGET_AVX512F")]) - (define_mode_iterator VI124_AVX512F [(V32QI "TARGET_AVX2") V16QI (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI @@ -9143,20 +9137,43 @@ "TARGET_SSE2" "operands[2] = force_reg (mode, CONST0_RTX (mode));") -(define_expand "3" +(define_expand "3" [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "nonimmediate_operand") (match_operand:VI_AVX2 2 "nonimmediate_operand")))] - "TARGET_SSE2 && " + "TARGET_SSE2" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_expand "3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (plusminus:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "nonimmediate_operand") + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) + (match_operand:VI48_AVX512VL 3 "vector_move_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512F" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_expand "3_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (plusminus:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand") + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) + (match_operand:VI12_AVX512VL 3 "vector_move_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512BW" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*3" +(define_insn "*3" [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") (plusminus:VI_AVX2 (match_operand:VI_AVX2 1 "nonimmediate_operand" "0,v") (match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands) && " + "TARGET_SSE2 + && ix86_binary_operator_ok (, mode, operands)" "@ p\t{%2, %0|%0, %2} vp\t{%2, %1, %0|%0, %1, %2}" @@ -9166,6 +9183,35 @@ (set_attr "prefix" "") (set_attr "mode" "")]) +(define_insn "*3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI48_AVX512VL + (plusminus:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "v") + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) + (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C") + (match_operand: 4 "register_operand" "Yk")))] + "TARGET_AVX512F + && ix86_binary_operator_ok (, mode, operands)" + "vp\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" + [(set_attr "type" "sseiadd") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*3_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12_AVX512VL + (plusminus:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "v") + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) + (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C") + (match_operand: 4 "register_operand" "Yk")))] + "TARGET_AVX512BW && ix86_binary_operator_ok (, mode, operands)" + "vp\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}" + [(set_attr "type" "sseiadd") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "_3" [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 @@ -10654,19 +10700,41 @@ operands[2] = force_reg (mode, gen_rtx_CONST_VECTOR (mode, v)); }) -(define_expand "_andnot3" +(define_expand "_andnot3" [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2 (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand")) (match_operand:VI_AVX2 2 "nonimmediate_operand")))] - "TARGET_SSE2 && ") + "TARGET_SSE2") -(define_insn "*andnot3" +(define_expand "_andnot3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (and:VI48_AVX512VL + (not:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand")) + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")) + (match_operand:VI48_AVX512VL 3 "vector_move_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512F") + +(define_expand "_andnot3_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand") + (vec_merge:VI12_AVX512VL + (and:VI12_AVX512VL + (not:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "register_operand")) + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")) + (match_operand:VI12_AVX512VL 3 "vector_move_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512BW") + +(define_insn "*andnot3" [(set (match_operand:VI 0 "register_operand" "=x,v") (and:VI (not:VI (match_operand:VI 1 "register_operand" "0,v")) (match_operand:VI 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE && " + "TARGET_SSE" { static char buf[64]; const char *ops; @@ -10740,7 +10808,7 @@ (eq_attr "mode" "TI")) (const_string "1") (const_string "*"))) - (set_attr "prefix" "") + (set_attr "prefix" "orig,vex") (set (attr "mode") (cond [(and (match_test " == 16") (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")) @@ -10758,6 +10826,36 @@ ] (const_string "")))]) +(define_insn "*andnot3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI48_AVX512VL + (and:VI48_AVX512VL + (not:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand" "v")) + (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")) + (match_operand:VI48_AVX512VL 3 "vector_move_operand" "0C") + (match_operand: 4 "register_operand" "Yk")))] + "TARGET_AVX512F" + "vpandn\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"; + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*andnot3_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12_AVX512VL + (and:VI12_AVX512VL + (not:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "register_operand" "v")) + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")) + (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C") + (match_operand: 4 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vpandn\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"; + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "3" [(set (match_operand:VI 0 "register_operand") (any_logic:VI @@ -13673,22 +13771,48 @@ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI")]) -(define_insn "abs2" - [(set (match_operand:VI124_AVX2_48_AVX512F 0 "register_operand" "=v") - (abs:VI124_AVX2_48_AVX512F - (match_operand:VI124_AVX2_48_AVX512F 1 "nonimmediate_operand" "vm")))] - "TARGET_SSSE3 && " - "%vpabs\t{%1, %0|%0, %1}" +(define_insn "*abs2" + [(set (match_operand:VI_AVX2 0 "register_operand" "=v") + (abs:VI_AVX2 + (match_operand:VI_AVX2 1 "nonimmediate_operand" "vm")))] + "TARGET_SSSE3" + "%vpabs\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") (set_attr "prefix_data16" "1") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) +(define_insn "abs2_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI48_AVX512VL + (abs:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "vm")) + (match_operand:VI48_AVX512VL 2 "vector_move_operand" "0C") + (match_operand: 3 "register_operand" "Yk")))] + "TARGET_AVX512F" + "vpabs\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "sselog1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "abs2_mask" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12_AVX512VL + (abs:VI12_AVX512VL + (match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "vm")) + (match_operand:VI12_AVX512VL 2 "vector_move_operand" "0C") + (match_operand: 3 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vpabs\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "sselog1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "abs2" - [(set (match_operand:VI124_AVX2_48_AVX512F 0 "register_operand") - (abs:VI124_AVX2_48_AVX512F - (match_operand:VI124_AVX2_48_AVX512F 1 "nonimmediate_operand")))] + [(set (match_operand:VI_AVX2 0 "register_operand") + (abs:VI_AVX2 + (match_operand:VI_AVX2 1 "nonimmediate_operand")))] "TARGET_SSE2" { if (!TARGET_SSSE3)