From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Sat, 2 Oct 2021 09:23:42 +0000 (+0000)
Subject: fixedlogical: simplify extsw
X-Git-Tag: sv_maxu_works-initial~778
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70550107a0cf3bfe6624d420789a0cb12f44ad4d;p=openpower-isa.git

fixedlogical: simplify extsw
---

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index 5162dbd4..b1332fe8 100644
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -389,9 +389,7 @@ X-Form
 
 Pseudo-code:
 
-    s <- (RS)[XLEN/2]
-    RA[XLEN/2:XLEN-1] <- (RS)[XLEN/2:XLEN-1]
-    RA[0:(XLEN/2)-1] <- [s]*(XLEN/2)
+    RA <- EXTSXL(RS, 32)
 
 Special Registers Altered: