From: H.J. Lu Date: Tue, 12 Feb 2019 19:00:35 +0000 (+0000) Subject: i386: Revert revision 268678 and revision 268657 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=705c92a2ab98d373c8500fd096cd49e8cc97c070;p=gcc.git i386: Revert revision 268678 and revision 268657 i386 backend has INT_MODE (OI, 32); INT_MODE (XI, 64); So, XI_MODE represents 64 INTEGER bytes = 64 * 8 = 512 bit operation, in case of const_1, all 512 bits set. We can load zeros with narrower instruction, (e.g. 256 bit by inherent zeroing of highpart in case of 128 bit xor), so TImode in this case. Some targets prefer V4SF mode, so they will emit float xorps for zeroing Then the introduction of AVX512F fubared everything by overloading the meaning of insn mode. How should we use INSN mode, MODE_XI, in standard_sse_constant_opcode and patterns which use standard_sse_constant_opcode? 2 options: 1. MODE_XI should only used to check if EXT_REX_SSE_REG_P is true in any register operand. The operand size must be determined by operand itself , not by MODE_XI. The operand encoding size should be determined by the operand size, EXT_REX_SSE_REG_P and AVX512VL. 2. MODE_XI should be used to determine the operand encoding size. EXT_REX_SSE_REG_P and AVX512VL should be checked for encoding instructions. gcc/ PR target/89229 * config/i386/i386.md (*movoi_internal_avx): Revert revision 268678 and revision 268657. (*movti_internal): Likewise. gcc/testsuite/ PR target/89229 * gcc.target/i386/pr89229-1.c: New test. From-SVN: r268811 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c90ff8a9d0..27b8b1dda5b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-02-12 H.J. Lu + + PR target/89229 + * config/i386/i386.md (*movoi_internal_avx): Revert revision + 268678 and revision 268657. + (*movti_internal): Likewise. + 2019-02-12 Ilya Leoshkevich PR target/89233 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3d9141ae450..9948f77fca5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1933,13 +1933,12 @@ (set_attr "type" "sselog1,sselog1,ssemov,ssemov") (set_attr "prefix" "vex") (set (attr "mode") - (cond [(and (not (match_test "TARGET_AVX512VL")) - (ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand"))) + (cond [(ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand")) (const_string "XI") (and (eq_attr "alternative" "1") (match_test "TARGET_AVX512VL")) - (const_string "OI") + (const_string "XI") (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") (and (eq_attr "alternative" "3") (match_test "TARGET_SSE_TYPELESS_STORES"))) @@ -2013,13 +2012,12 @@ (set (attr "mode") (cond [(eq_attr "alternative" "0,1") (const_string "DI") - (and (not (match_test "TARGET_AVX512VL")) - (ior (match_operand 0 "ext_sse_reg_operand") - (match_operand 1 "ext_sse_reg_operand"))) + (ior (match_operand 0 "ext_sse_reg_operand") + (match_operand 1 "ext_sse_reg_operand")) (const_string "XI") (and (eq_attr "alternative" "3") (match_test "TARGET_AVX512VL")) - (const_string "TI") + (const_string "XI") (ior (not (match_test "TARGET_SSE2")) (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") (and (eq_attr "alternative" "5") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7cb2c414489..d8549f0fb3e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-02-12 H.J. Lu + + PR target/89229 + * gcc.target/i386/pr89229-1.c: New test. + 2019-02-12 Ilya Leoshkevich PR target/89233 diff --git a/gcc/testsuite/gcc.target/i386/pr89229-1.c b/gcc/testsuite/gcc.target/i386/pr89229-1.c new file mode 100644 index 00000000000..cce95350bf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr89229-1.c @@ -0,0 +1,47 @@ +/* { dg-do assemble { target { avx512bw && avx512vl } } } */ +/* { dg-options "-O1 -mavx512bw -mavx512vl -mtune=skylake-avx512" } */ + +extern void abort (void); +extern void exit (int); +struct s { unsigned char a[256]; }; +union u { struct { struct s b; int c; } d; struct { int c; struct s b; } e; }; +static union u v; +static union u v0; +static struct s *p = &v.d.b; +static struct s *q = &v.e.b; + +static inline struct s rp (void) { return *p; } +static inline struct s rq (void) { return *q; } +static void pq (void) { *p = rq(); } +static void qp (void) { *q = rp(); } + +static void +init (struct s *sp) +{ + int i; + for (i = 0; i < 256; i++) + sp->a[i] = i; +} + +static void +check (struct s *sp) +{ + int i; + for (i = 0; i < 256; i++) + if (sp->a[i] != i) + abort (); +} + +void +main_test (void) +{ + v = v0; + init (p); + qp (); + check (q); + v = v0; + init (q); + pq (); + check (p); + exit (0); +}