From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 21:14:46 +0000 (-0800)
Subject: Add a quick testcase for unknown modules as inout
X-Git-Tag: working-ls180~778^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=705e520a527864dc32f1934bb4b2b94d75f8f0ec;p=yosys.git

Add a quick testcase for unknown modules as inout
---

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 9d7dabdd7..4fb45043b 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -80,9 +80,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 
-
 design -reset
-read_verilog -icells <<EOT
+read_verilog <<EOT
 module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
 (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
 DFF s2(.D(d), .C(c), .Q(q[0]));
@@ -100,3 +99,26 @@ proc
 submod
 dffinit -ff DFF Q INIT
 check -noinit -assert
+
+
+design -reset
+read_verilog <<EOT
+module top(input d, c, output reg [2:0] q);
+(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
+DFF s2(.D(d), .C(c), .Q(q[0]));
+DFF s3(.D(d), .C(c), .Q(q[2]));
+endmodule
+EOT
+
+hierarchy -top top
+proc
+
+submod
+flatten
+
+read_verilog <<EOT
+module DFF(input D, C, output Q);
+endmodule
+EOT
+
+check -assert