From: Andreas Sandberg <Andreas.Sandberg@ARM.com>
Date: Tue, 5 May 2015 07:22:34 +0000 (-0400)
Subject: arm: Relax ordering for some uncacheable accesses
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=706597f021811511e71fddeeab7dcfc33bfd5f35;p=gem5.git

arm: Relax ordering for some uncacheable accesses

We currently assume that all uncacheable memory accesses are strictly
ordered. Instead of always enforcing strict ordering, we now only
enforce it if the required memory type is device memory or strongly
ordered memory.
---

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 8c3bb047d..61c2eb9d6 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1076,7 +1076,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
         setAttr(te->attributes);
 
         if (te->nonCacheable)
-            req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
+            req->setFlags(Request::UNCACHEABLE);
+
+        // Require requests to be ordered if the request goes to
+        // strongly ordered or device memory (i.e., anything other
+        // than normal memory requires strict order).
+        if (te->mtype != TlbEntry::MemoryType::Normal)
+            req->setFlags(Request::STRICT_ORDER);
 
         Addr pa = te->pAddr(vaddr);
         req->setPaddr(pa);