From: Nilay Vaish Date: Wed, 19 Nov 2014 01:17:29 +0000 (-0600) Subject: configs: small fix to ruby portion of fs.py and se.py X-Git-Tag: stable_2015_04_15~120 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=708e80d9bb0577662dd7181d4ae947c2cc9b8ac9;p=gem5.git configs: small fix to ruby portion of fs.py and se.py In fs.py the io port controller was being attached to the iobus multiple times. This should be done only once. In se.py, the the option use_map was being set which no longer exists. --- diff --git a/configs/example/fs.py b/configs/example/fs.py index 727f69339..0277feef3 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -142,6 +142,10 @@ def build_test_system(np): test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = test_sys.voltage_domain) + # Connect the ruby io port to the PIO bus, + # assuming that there is just one such port. + test_sys.iobus.master = test_sys.ruby._io_port.slave + for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports @@ -161,10 +165,6 @@ def build_test_system(np): cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master - # Connect the ruby io port to the PIO bus, - # assuming that there is just one such port. - test_sys.iobus.master = test_sys.ruby._io_port.slave - else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock diff --git a/configs/example/se.py b/configs/example/se.py index e0535c726..83eabdc83 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -225,7 +225,6 @@ if options.ruby: print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) - options.use_map = True Ruby.create_system(options, False, system) assert(options.num_cpus == len(system.ruby._cpu_ports))