From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 29 Nov 2012 22:47:51 +0000 (+0100)
Subject: corelogic/roundrobin: fix request width (again)
X-Git-Tag: 24jan2021_ls180~2099^2~731
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7093939309a0d0d77f1dc78ba0f5a12826a37010;p=litex.git

corelogic/roundrobin: fix request width (again)
---

diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index 298c7d16..f55b3fee 100644
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 class RoundRobin:
 	def __init__(self, n, switch_policy=SP_WITHDRAW):
 		self.n = n
-		self.request = Signal(nbits=self.n)
+		self.request = Signal(self.n)
 		self.grant = Signal(max=self.n)
 		self.switch_policy = switch_policy
 		if self.switch_policy == SP_CE: