From: lkcl <lkcl@web>
Date: Fri, 6 Aug 2021 12:34:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~475
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7095c7c48665a2f28f793ea9e021c3740a6c3b95;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index ae1aa670c..d86dd398f 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -51,13 +51,13 @@ with the pseudocode below, the immediate can be used to give unit stride or elem
         if (RA.isvec) while (!(ps & 1<<i)) i++;
         if (RAupdate.isvec) while (!(ps & 1<<u)) u++;
         if (RT.isvec) while (!(pd & 1<<j)) j++;
-        if svctx.ldstmode == bitreversed: # for FFT/DCT
-          # FFT/DCT bitreversed mode
+        if svctx.ldstmode == shifted: # for FFT/DCT
+          # FFT/DCT shifted mode
           if (RA.isvec)
             srcbase = ireg[RA+i]
           else
             srcbase = ireg[RA]
-          offs = (bitrev(i, VL) * immed) << RC
+          offs = (i * immed) << RC
         elif svctx.ldstmode == elementstride:
           # element stride mode
           srcbase = ireg[RA]