From: lkcl Date: Thu, 25 Mar 2021 15:08:21 +0000 (+0000) Subject: (no commit message) X-Git-Tag: DRAFT_SVP64_0_1~1150 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=709e482fc2d98be1cfc57feae830f7dc5d25980b;p=libreriscv.git --- diff --git a/openpower/ISA_WG/Board_letter_26mar2021.mdwn b/openpower/ISA_WG/Board_letter_26mar2021.mdwn index a10836360..bd7a6628f 100644 --- a/openpower/ISA_WG/Board_letter_26mar2021.mdwn +++ b/openpower/ISA_WG/Board_letter_26mar2021.mdwn @@ -22,7 +22,7 @@ to be sent to: Dear OPF Board, -As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs. RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the decades, SIMD has been demonstrated to be harmful. +As you know the LibreSOC team have been working for over 3 years on a massive conceptual upgrade to the OpenPOWER ISA, based on Cray-Style Vectors, which will modernise it for today's 3D and VPU workloads, with an incidental side-effect of upgrading it for future supercomputing needs over the next few decades in a clean and elegant fashion. RISC-V has RVV, ARM has SVE2, x86 has AVX512, whilst OpenPOWER has an out-of-date SIMD ISA. It goes without saying that over the decades, SIMD has been demonstrated to be harmful. https://www.sigarch.org/simd-instructions-considered-harmful/