From: Luke Kenneth Casson Leighton Date: Sun, 5 Jul 2020 12:18:03 +0000 (+0100) Subject: move valid signal out of Decode2ToExecute1Type and into PowerDecoder2 X-Git-Tag: div_pipeline~162^2~65 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70a9337a68b13ea4daeee7e8af5141c928da1ea6;p=soc.git move valid signal out of Decode2ToExecute1Type and into PowerDecoder2 --- diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index b0274e3a..75e29e1b 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -29,7 +29,6 @@ class Decode2ToExecute1Type(RecordObject): RecordObject.__init__(self, name=name) - self.valid = Signal(reset_less=True) self.insn_type = Signal(InternalOp, reset_less=True) self.fn_unit = Signal(Function, reset_less=True) if asmcode: diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 767ca50a..5fd01058 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -543,6 +543,7 @@ class PowerDecode2(Elaboratable): self.dec = dec self.e = Decode2ToExecute1Type() + self.valid = Signal() def ports(self): return self.dec.ports() + self.e.ports() diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 8e4ff93f..04211107 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -70,7 +70,7 @@ class NonProductionCore(Elaboratable): self.pdecode2 = PowerDecode2(pdecode) # instruction decoder # issue/valid/busy signalling - self.ivalid_i = self.pdecode2.e.valid # instruction is valid + self.ivalid_i = self.pdecode2.valid # instruction is valid self.issue_i = Signal(reset_less=True) self.busy_o = Signal(name="corebusy_o", reset_less=True)