From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 20 Sep 2022 00:45:48 +0000 (+0300)
Subject: power_insn: support vs/vsi/vsb/vsbi/ctr/cti specifiers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70ac339ca3f951551e917598908990a504bbe6e7;p=openpower-isa.git

power_insn: support vs/vsi/vsb/vsbi/ctr/cti specifiers
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 073d4d77..98fd44c9 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1758,11 +1758,29 @@ class BranchVLSRM(BranchBaseRM):
     VSb: BaseRM[7]
     VLI: BaseRM[21]
 
+    def specifiers(self, record):
+        yield {
+            (0b0, 0b0): "vs",
+            (0b0, 0b1): "vsi",
+            (0b1, 0b0): "vsb",
+            (0b1, 0b1): "vsbi",
+        }[int(self.VSb), int(self.VLI)]
+
+        yield from super().specifiers(record=record)
+
 
 class BranchCTRRM(BranchBaseRM):
     """branch: CTR-test mode"""
     CTi: BaseRM[6]
 
+    def specifiers(self, record):
+        if self.CTi:
+            yield "cti"
+        else:
+            yield "ctr"
+
+        yield from super().specifiers(record=record)
+
 
 class BranchCTRVLSRM(BranchVLSRM, BranchCTRRM):
     """branch: CTR-test+VLSET mode"""
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 7e1b2637..da0e8e55 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1154,12 +1154,10 @@ class SVP64Asm:
                     svp64_rm.branch.vls.VSb = 1
                 elif encmode == 'vsbi':
                     svp64_rm.branch.VLS = 1
-                    svp64_rm.branch.vls.VLb = 1
+                    svp64_rm.branch.vls.VSb = 1
                     svp64_rm.branch.vls.VLI = 1
                 elif encmode == 'ctr':
                     svp64_rm.branch.CTR = 1
-                    svp64_rm.branch.VLS = 0
-                    svp64_rm.branch.ctr.CTi = 1
                 elif encmode == 'cti':
                     svp64_rm.branch.CTR = 1
                     svp64_rm.branch.ctr.CTi = 1
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 53d854ca..981147e1 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -261,6 +261,12 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.bc/snz 12,*1,0xc",
                     "sv.bc/all/sl/slu 12,*1,0xc",
                     "sv.bc/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vs/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsi/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsb/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc",
                         ]
         self._do_tst(expected)