From: Megan Wachs <megan@sifive.com>
Date: Fri, 31 Mar 2017 20:49:34 +0000 (-0700)
Subject: spi: correct polarity of FIRRTL combo loop detection workaround.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70ac4044d1cfeb801ca4e16bc32da6339e82c1ab;p=sifive-blocks.git

spi: correct polarity of FIRRTL combo loop detection workaround.
---

diff --git a/src/main/scala/devices/spi/SPIArbiter.scala b/src/main/scala/devices/spi/SPIArbiter.scala
index df87d95..3c0c74a 100644
--- a/src/main/scala/devices/spi/SPIArbiter.scala
+++ b/src/main/scala/devices/spi/SPIArbiter.scala
@@ -21,7 +21,7 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
   io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
   io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
   // Workaround for overzealous combinational loop detection
-  io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs)
+  io.outer.cs := Mux(sel(0), io.inner(0).cs, io.inner(1).cs)
   require(n == 2, "SPIArbiter currently only supports 2 clients")
 
   (io.inner zip sel).foreach { case (inner, s) =>