From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 28 Mar 2020 17:18:36 +0000 (+0000)
Subject: add condition page
X-Git-Tag: convert-csv-opcode-to-binary~3044
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70bdff709edbc594a0ed12bc202f228f85a0ae89;p=libreriscv.git

add condition page
---

diff --git a/openpower/isa/condition.mdwn b/openpower/isa/condition.mdwn
new file mode 100644
index 000000000..4f181d0e3
--- /dev/null
+++ b/openpower/isa/condition.mdwn
@@ -0,0 +1,56 @@
+# Condition Register AND
+
+crand BT,BA,BB
+
+    CR[BT+32] <-  CR[BA+32] & CR[BB+32]
+
+# Condition Register NAND
+
+crnand BT,BA,BB
+
+    CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
+
+# Condition Register OR
+
+cror BT,BA,BB
+
+    CR[BT+32] <-  CR[BA+32] | CR[BB+32]
+
+Condition Register XOR
+
+crxor     BT,BA,BB
+
+    CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
+
+# Condition Register NOR
+
+crnor BT,BA,BB
+
+    CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
+
+# Condition Register Equivalent
+
+creqv BT,BA,BB
+
+    CR[BT+32] <- CR[BA+32] => CR[BB+32]
+
+# Condition Register AND with Complement 
+
+crandc BT,BA,BB
+
+    CR[BT+32] <- CR[BA+32] &  ¬CR[BB+32]
+
+# Condition Register OR with Complement
+
+crorc BT,BA,BB
+
+    CR[BT+32] <- CR[BA+32] |  ¬CR[BB+32]
+
+
+# Move Condition Register Field
+
+mcrf BF,BFA
+
+    CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
+
+