From: Megan Wachs <megan@sifive.com>
Date: Sun, 20 Aug 2017 19:39:38 +0000 (-0700)
Subject: spi: Make memory mapped interface depth a parameter
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70c25846b8290376fd3851cb896d2eb91f2bb5b1;p=sifive-blocks.git

spi: Make memory mapped interface depth a parameter
---

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 6e58647..595ffc3 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -43,7 +43,7 @@ trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
     qspi.rnode := pbus.toVariableWidthSlaves
     qspi.fnode :=
       TLFragmenter(1, pbus.blockBytes)(
-      TLBuffer(BufferParams(8), BufferParams.none)(
+      TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
       pbus.toFixedWidthSlaves))
     ibus.fromSync := qspi.intnode
     qspi
diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala
index bfec1d1..e433fec 100644
--- a/src/main/scala/devices/spi/TLSPIFlash.scala
+++ b/src/main/scala/devices/spi/TLSPIFlash.scala
@@ -11,6 +11,7 @@ import freechips.rocketchip.util.HeterogeneousBag
 trait SPIFlashParamsBase extends SPIParamsBase {
   val fAddress: BigInt
   val fSize: BigInt
+  val fBufferDepth: Int
 
   val insnAddrBytes: Int
   val insnPadLenBits: Int
@@ -22,6 +23,7 @@ trait SPIFlashParamsBase extends SPIParamsBase {
 case class SPIFlashParams(
     rAddress: BigInt,
     fAddress: BigInt,
+    fBufferDepth: Int = 0,
     rSize: BigInt = 0x1000,
     fSize: BigInt = 0x20000000,
     rxDepth: Int = 8,