From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:07:54 +0000 (-0700)
Subject: Update doc
X-Git-Tag: working-ls180~1039^2~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70c5444b25f18760781509104f4393b3d0a05fc0;p=yosys.git

Update doc
---

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index cff4c5ddb..0b7ffe64b 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -288,8 +288,8 @@ struct Ice40DspPass : public Pass {
 		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
 		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
-		log("({F,J,K,G}, H), output registers (O; with optional hold), and post-adder into\n");
-		log("into the SB_MAC16 resource.\n");
+		log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
+		log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");