From: Luke Kenneth Casson Leighton Date: Mon, 12 Feb 2024 10:21:06 +0000 (+0000) Subject: bug 676: add /mr to sv.minmax. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70cb52dad1c9a56dff9dcacef3df2543b88ecd0e;p=openpower-isa.git bug 676: add /mr to sv.minmax. --- diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py index 1a49e0a1..e8c0d316 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py @@ -8,6 +8,7 @@ Funded by NLnet NGI-ASSURE under EU grant agreement No 957073. """ import unittest +import random from copy import deepcopy from nmutil.formaltest import FHDLTestCase @@ -57,15 +58,33 @@ class DDFFirstTestCase(FHDLTestCase): def test_sv_maxloc_1(self): self.sv_maxloc([1,3,3,3]) - def tst_sv_maxloc_2(self): + def test_sv_maxloc_2(self): self.sv_maxloc([3,4,1,5]) - def tst_sv_maxloc_3(self): + def test_sv_maxloc_3(self): self.sv_maxloc([2,9,8,0]) - def tst_sv_maxloc_4(self): + def test_sv_maxloc_4(self): self.sv_maxloc([2,1,3,0]) + def test_sv_maxloc_5(self): + self.sv_maxloc([0,0,0,0]) + + def test_sv_maxloc_6(self): + self.sv_maxloc([0,9,9,3]) + + def test_sv_maxloc_7(self): + self.sv_maxloc([9,0,10,11]) + + def test_sv_maxloc_random(self): + random.seed(1) # set the same seed (consistent test) + for i in range(50): + array = [] + for j in range(4): + array.append(random.randint(0, 20)) + with self.subTest(i=i): + self.sv_maxloc(array) + def sv_maxloc(self, ra): """ m, nm, i, n = 0, 0, 0, len(a) @@ -82,21 +101,21 @@ class DDFFirstTestCase(FHDLTestCase): # represented as a bitmask (CR bits 16,20,24,28) lst = SVP64Asm([ - # while (im): - "sv.minmax./ff=le/m=ge 4,*10,4,1", # uses r4 as accumulator - "crternlogi 0,1,2,127", # test greater/equal or VL=0 - "sv.crand *19,*16,0", # clear if CR0.eq=0 - # nm = i (count masked bits. could use crweirds here TODO) - "sv.svstep/mr/m=so 1, 0, 6, 1", # svstep: get vector dststep - "sv.creqv *16,*16,*16", # set mask on already-tested - "bc 12,0, -0x40" # CR0 lt bit clear, branch back + # while (im): + "sv.minmax./ff=le/m=ge/mr 4,*10,4,1", # uses r4 as accumulator + "crternlogi 0,1,2,127", # test greater/equal or VL=0 + "sv.crand *19,*16,0", # clear if CR0.eq=0 + # nm = i (count masked bits. could use crweirds here TODO) + "sv.svstep/mr/m=so 1, 0, 6, 1", # svstep: get vector dststep + "sv.creqv *16,*16,*16", # set mask on already-tested + "bc 12,0, -0x40" # CR0 lt bit clear, branch back ]) lst = list(lst)