From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 1 Feb 2009 08:26:10 +0000 (-0800)
Subject: X86: Configure the first PCI interrupt.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70cd5bfce5549495c6e969fa509bfd5f56190e10;p=gem5.git

X86: Configure the first PCI interrupt.
---

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 3d1c9bd9e..e336e752f 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -212,6 +212,19 @@ def makeX86System(mem_mode, mdesc = None, self = None):
     self.intel_mp_table.add_entry(io_apic)
     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
     self.intel_mp_table.add_entry(isa_bus)
+    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
+    self.intel_mp_table.add_entry(pci_bus)
+    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
+            subtractive_decode=True, parent_bus=1)
+    self.intel_mp_table.add_entry(connect_busses)
+    pci_dev4_inta = X86IntelMPIOIntAssignment(
+            interrupt_type = 'INT',
+            polarity = 'ConformPolarity',
+            trigger = 'ConformTrigger',
+            source_bus_id = 1,
+            source_bus_irq = 0 + (4 << 2),
+            dest_io_apic_id = 1,
+            dest_io_apic_intin = 16)
     assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
             interrupt_type = 'ExtInt',
             polarity = 'ConformPolarity',
@@ -266,6 +279,24 @@ def makeX86System(mem_mode, mdesc = None, self = None):
             dest_io_apic_id = 1,
             dest_io_apic_intin = 12)
     self.intel_mp_table.add_entry(assign_12_to_apic)
+    assign_8259_14_to_apic = X86IntelMPIOIntAssignment(
+            interrupt_type = 'ExtInt',
+            polarity = 'ConformPolarity',
+            trigger = 'ConformTrigger',
+            source_bus_id = 0,
+            source_bus_irq = 14,
+            dest_io_apic_id = 1,
+            dest_io_apic_intin = 0)
+    self.intel_mp_table.add_entry(assign_8259_14_to_apic)
+    assign_14_to_apic = X86IntelMPIOIntAssignment(
+            interrupt_type = 'INT',
+            polarity = 'ConformPolarity',
+            trigger = 'ConformTrigger',
+            source_bus_id = 0,
+            source_bus_irq = 14,
+            dest_io_apic_id = 1,
+            dest_io_apic_intin = 14)
+    self.intel_mp_table.add_entry(assign_14_to_apic)
 
 
 def makeLinuxX86System(mem_mode, mdesc = None):
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 8d766471e..d89ed9dc6 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -87,7 +87,8 @@ class SouthBridge(SimObject):
     ide.BAR3LegacyIO = True
     ide.BAR4 = 1
     ide.Command = 1
-    ide.InterruptLine = 20
+    ide.InterruptLine = 14
+    ide.InterruptPin = 1
 
     def attachIO(self, bus):
         # Route interupt signals
diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index 5005bd296..d23474c67 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -101,6 +101,12 @@ Pc::init()
     entry.vector = 0x2C;
     ioApic.writeReg(0x28, entry.bottomDW);
     ioApic.writeReg(0x29, entry.topDW);
+    entry.vector = 0x2E;
+    ioApic.writeReg(0x2C, entry.bottomDW);
+    ioApic.writeReg(0x2D, entry.topDW);
+    entry.vector = 0x30;
+    ioApic.writeReg(0x30, entry.bottomDW);
+    ioApic.writeReg(0x31, entry.topDW);
 }
 
 Tick