From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 19:58:25 +0000 (+0200)
Subject: Merge pull request #988 from YosysHQ/clifford/fix987
X-Git-Tag: yosys-0.9~150
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70d0f389ad6e7e0ad762b62d3a626a4db5b23827;p=yosys.git

Merge pull request #988 from YosysHQ/clifford/fix987

Add approximate support for SV "var" keyword
---

70d0f389ad6e7e0ad762b62d3a626a4db5b23827
diff --cc frontends/verilog/verilog_lexer.l
index e97632663,59ef3e36e..08e556e8e
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@@ -206,8 -206,8 +206,9 @@@ YOSYS_NAMESPACE_EN
  "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
  "checker"    { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
  "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
 +"final"      { SV_KEYWORD(TOK_FINAL); }
  "logic"      { SV_KEYWORD(TOK_LOGIC); }
+ "var"        { SV_KEYWORD(TOK_VAR); }
  "bit"        { SV_KEYWORD(TOK_REG); }
  
  "eventually"   { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }