From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Tue, 28 Nov 2023 17:18:16 +0000 (+0000)
Subject: Add more info
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70d8dcac7bb4553d0d6e855d577378e94e69061a;p=libreriscv.git

Add more info
---

diff --git a/meetings/sync_up/sync_up_2023-11-28.mdwn b/meetings/sync_up/sync_up_2023-11-28.mdwn
index 86dcdadbe..9c377256c 100644
--- a/meetings/sync_up/sync_up_2023-11-28.mdwn
+++ b/meetings/sync_up/sync_up_2023-11-28.mdwn
@@ -24,6 +24,10 @@
   See [[meetings/dmitry_2023-11-24]] notes for more context.
 
 - RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
+- The first step is to make modifications to `svanalysis.py` to classify the RISC-V instructions.
+- Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
+- Invent an opcode format?
+
 
 # Dmitry