From: Sebastien Bourdeauducq Date: Wed, 22 May 2013 15:11:09 +0000 (+0200) Subject: New migen.fhdl.std to simplify imports + len->flen X-Git-Tag: 24jan2021_ls180~2099^2~574 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=70ffe86356f927460094fee2a57afc06177cc0c3;p=litex.git New migen.fhdl.std to simplify imports + len->flen --- diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py index 7792dc91..2822e197 100644 --- a/examples/basic/arrays.py +++ b/examples/basic/arrays.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Instance -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog class Example(Module): diff --git a/examples/basic/complex.py b/examples/basic/complex.py index d632fe44..f5777103 100644 --- a/examples/basic/complex.py +++ b/examples/basic/complex.py @@ -1,4 +1,4 @@ -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.complex import * from migen.fhdl import verilog diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py index 5dfc4f76..eb7e03ae 100644 --- a/examples/basic/fsm.py +++ b/examples/basic/fsm.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog from migen.genlib.fsm import FSM diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py index f623fbf7..3a543e5f 100644 --- a/examples/basic/graycounter.py +++ b/examples/basic/graycounter.py @@ -1,6 +1,6 @@ from random import Random -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import GrayCounter from migen.sim.generic import Simulator diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py index bebd920e..ca7dd842 100644 --- a/examples/basic/local_cd.py +++ b/examples/basic/local_cd.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog from migen.genlib.divider import Divider diff --git a/examples/basic/memory.py b/examples/basic/memory.py index d3c8f771..19e011ab 100644 --- a/examples/basic/memory.py +++ b/examples/basic/memory.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import Fragment -from migen.fhdl.specials import Memory -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog class Example(Module): diff --git a/examples/basic/namer.py b/examples/basic/namer.py index eb6c5ee2..e722dcb4 100644 --- a/examples/basic/namer.py +++ b/examples/basic/namer.py @@ -1,6 +1,5 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.fhdl import verilog -from migen.fhdl.module import Module from migen.genlib.misc import optree def gen_list(n): diff --git a/examples/basic/psync.py b/examples/basic/psync.py index 59422d5e..8bbb3f45 100644 --- a/examples/basic/psync.py +++ b/examples/basic/psync.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.fhdl.specials import SynthesisDirective from migen.fhdl import verilog from migen.genlib.cdc import * diff --git a/examples/basic/record.py b/examples/basic/record.py index dd7a905b..aec89c64 100644 --- a/examples/basic/record.py +++ b/examples/basic/record.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog from migen.genlib.record import * diff --git a/examples/basic/simple_gpio.py b/examples/basic/simple_gpio.py index cb8a3a8f..ab2502ee 100644 --- a/examples/basic/simple_gpio.py +++ b/examples/basic/simple_gpio.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog from migen.genlib.cdc import MultiReg from migen.bank import description, csrgen diff --git a/examples/basic/tristate.py b/examples/basic/tristate.py index b9c867d3..47696fd3 100644 --- a/examples/basic/tristate.py +++ b/examples/basic/tristate.py @@ -1,16 +1,11 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Tristate -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog class Example(Module): def __init__(self, n=6): self.pad = Signal(n) - self.o = Signal(n) - self.oe = Signal() - self.i = Signal(n) - - self.specials += Tristate(self.pad, self.o, self.oe, self.i) + self.t = TSTriple(n) + self.specials += self.t.get_tristate(self.pad) e = Example() -print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i})) +print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i})) diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py index b474fa34..98759419 100644 --- a/examples/basic/two_dividers.py +++ b/examples/basic/two_dividers.py @@ -1,5 +1,5 @@ +from migen.fhdl.std import * from migen.fhdl import verilog -from migen.fhdl.module import Module from migen.genlib import divider class Example(Module): diff --git a/examples/dataflow/dma.py b/examples/dataflow/dma.py index c46ee4a6..9ae85ab4 100644 --- a/examples/dataflow/dma.py +++ b/examples/dataflow/dma.py @@ -1,6 +1,6 @@ from random import Random -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.network import * from migen.flow.transactions import * from migen.actorlib import dma_wishbone, dma_asmi diff --git a/examples/pytholite/uio.py b/examples/pytholite/uio.py index edf26af0..c627a8ef 100644 --- a/examples/pytholite/uio.py +++ b/examples/pytholite/uio.py @@ -7,8 +7,7 @@ from migen.genlib.ioo import UnifiedIOSimulation from migen.pytholite.transel import Register from migen.pytholite.compiler import Pytholite from migen.sim.generic import Simulator -from migen.fhdl.module import Module -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.fhdl import verilog layout = [("r", 32)] diff --git a/examples/sim/abstract_transactions.py b/examples/sim/abstract_transactions.py index bb69169d..0922d04a 100644 --- a/examples/sim/abstract_transactions.py +++ b/examples/sim/abstract_transactions.py @@ -1,10 +1,6 @@ -# Copyright (C) 2012 Vermeer Manufacturing Co. -# License: GPLv3 with additional permissions (see README). - from random import Random -from migen.fhdl.structure import * -from migen.fhdl import autofragment +from migen.fhdl.std import * from migen.bus.transactions import * from migen.bus import wishbone, asmibus from migen.sim.generic import Simulator diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py index 8cf4b4c2..6890b170 100644 --- a/examples/sim/basic1.py +++ b/examples/sim/basic1.py @@ -1,7 +1,7 @@ # Copyright (C) 2012 Vermeer Manufacturing Co. # License: GPLv3 with additional permissions (see README). -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.sim.generic import Simulator # Our simple counter, which increments at every cycle diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py index 78fd2eeb..3b9aa7f2 100644 --- a/examples/sim/basic2.py +++ b/examples/sim/basic2.py @@ -1,7 +1,7 @@ # Copyright (C) 2012 Vermeer Manufacturing Co. # License: GPLv3 with additional permissions (see README). -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.sim.generic import Simulator, TopLevel # A slightly improved counter. diff --git a/examples/sim/dataflow.py b/examples/sim/dataflow.py index 4c02b24f..ca142344 100644 --- a/examples/sim/dataflow.py +++ b/examples/sim/dataflow.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.transactions import * from migen.flow.network import * diff --git a/examples/sim/fir.py b/examples/sim/fir.py index edce5a07..0f939403 100644 --- a/examples/sim/fir.py +++ b/examples/sim/fir.py @@ -5,8 +5,7 @@ from math import cos, pi from scipy import signal import matplotlib.pyplot as plt -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import verilog from migen.genlib.misc import optree from migen.sim.generic import Simulator diff --git a/examples/sim/memory.py b/examples/sim/memory.py index 44330179..45341d7e 100644 --- a/examples/sim/memory.py +++ b/examples/sim/memory.py @@ -1,8 +1,7 @@ # Copyright (C) 2012 Vermeer Manufacturing Co. # License: GPLv3 with additional permissions (see README). -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.sim.generic import Simulator class Mem: diff --git a/migen/actorlib/dma_asmi.py b/migen/actorlib/dma_asmi.py index 0220433a..142b2a10 100644 --- a/migen/actorlib/dma_asmi.py +++ b/migen/actorlib/dma_asmi.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * from migen.genlib.buffers import ReorderBuffer @@ -49,7 +48,7 @@ class OOOReader(Module): ### - tag_width = len(port.tag_call) + tag_width = flen(port.tag_call) data_width = port.hub.dw depth = len(port.slots) rob = ReorderBuffer(tag_width, data_width, depth) diff --git a/migen/actorlib/dma_wishbone.py b/migen/actorlib/dma_wishbone.py index c3551a3b..c86dd840 100644 --- a/migen/actorlib/dma_wishbone.py +++ b/migen/actorlib/dma_wishbone.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import wishbone from migen.flow.actor import * diff --git a/migen/actorlib/misc.py b/migen/actorlib/misc.py index f1d95acb..b99ad2e5 100644 --- a/migen/actorlib/misc.py +++ b/migen/actorlib/misc.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.record import * from migen.genlib.fsm import * from migen.flow.actor import * diff --git a/migen/actorlib/sim.py b/migen/actorlib/sim.py index 8c6463b4..ac80a2f0 100644 --- a/migen/actorlib/sim.py +++ b/migen/actorlib/sim.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.transactions import * diff --git a/migen/actorlib/spi.py b/migen/actorlib/spi.py index 38c51772..0f3a577e 100644 --- a/migen/actorlib/spi.py +++ b/migen/actorlib/spi.py @@ -1,7 +1,6 @@ # Simple Processor Interface -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.bank.description import * from migen.flow.actor import * from migen.flow.network import * @@ -130,8 +129,8 @@ class _DMAController(Module): class DMAReadController(_DMAController): def __init__(self, bus_accessor, *args, **kwargs): - bus_aw = len(bus_accessor.address.payload.a) - bus_dw = len(bus_accessor.data.payload.d) + bus_aw = flen(bus_accessor.address.payload.a) + bus_dw = flen(bus_accessor.data.payload.d) _DMAController.__init__(self, bus_accessor, bus_aw, bus_dw, *args, **kwargs) g = DataFlowGraph() diff --git a/migen/actorlib/structuring.py b/migen/actorlib/structuring.py index dd917bbc..e671fed0 100644 --- a/migen/actorlib/structuring.py +++ b/migen/actorlib/structuring.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * def _rawbits_layout(l): @@ -22,7 +21,7 @@ class Cast(CombinatorialActor): sigs_to = self.source.payload.flatten() if reverse_to: sigs_to = list(reversed(sigs_to)) - if sum(len(s) for s in sigs_from) != sum(len(s) for s in sigs_to): + if sum(flen(s) for s in sigs_from) != sum(flen(s) for s in sigs_to): raise TypeError self.comb += Cat(*sigs_to).eq(Cat(*sigs_from)) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index 01e4bf0f..836a499e 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -1,7 +1,6 @@ from operator import itemgetter -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus import csr from migen.bank.description import * diff --git a/migen/bank/description.py b/migen/bank/description.py index 92dcdcd2..d4141ebd 100644 --- a/migen/bank/description.py +++ b/migen/bank/description.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory -from migen.fhdl.module import * +from migen.fhdl.std import * from migen.fhdl.tracer import get_obj_var_name class _CSRBase(HUID): diff --git a/migen/bank/eventmanager.py b/migen/bank/eventmanager.py index 85e4476b..9c9aa423 100644 --- a/migen/bank/eventmanager.py +++ b/migen/bank/eventmanager.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * from migen.genlib.misc import optree diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py index 535acc32..e1141e98 100644 --- a/migen/bus/asmibus.py +++ b/migen/bus/asmibus.py @@ -1,5 +1,5 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module, FinalizeError +from migen.fhdl.std import * +from migen.fhdl.module import FinalizeError from migen.genlib.misc import optree from migen.genlib import roundrobin from migen.bus.transactions import * diff --git a/migen/bus/csr.py b/migen/bus/csr.py index 1c3c3bd4..dc51f7e5 100644 --- a/migen/bus/csr.py +++ b/migen/bus/csr.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus.transactions import * from migen.bank.description import CSRStorage from migen.genlib.record import * @@ -115,10 +113,10 @@ class SRAM(Module): ] if self._page is None: - self.comb += port.adr.eq(self.bus.adr[word_bits:len(port.adr)]) + self.comb += port.adr.eq(self.bus.adr[word_bits:flen(port.adr)]) else: pv = self._page.storage - self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:len(port.adr)-len(pv)], pv)) + self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:flen(port.adr)-flen(pv)], pv)) def get_csrs(self): if self._page is None: diff --git a/migen/bus/dfi.py b/migen/bus/dfi.py index d8c2f90f..42425b1b 100644 --- a/migen/bus/dfi.py +++ b/migen/bus/dfi.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.record import * def phase_description(a, ba, d): diff --git a/migen/bus/memory.py b/migen/bus/memory.py index c99f0e72..77aeaedb 100644 --- a/migen/bus/memory.py +++ b/migen/bus/memory.py @@ -1,4 +1,4 @@ -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bus.transactions import * def _byte_mask(orig, dat_w, sel): diff --git a/migen/bus/transactions.py b/migen/bus/transactions.py index a3dd4840..b3fc1cbf 100644 --- a/migen/bus/transactions.py +++ b/migen/bus/transactions.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import bits_for +from migen.fhdl.std import * class Transaction: def __init__(self, address, data=0, sel=None, busname=None): diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py index 5df37a92..a2550c42 100644 --- a/migen/bus/wishbone.py +++ b/migen/bus/wishbone.py @@ -1,6 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib import roundrobin from migen.genlib.record import * from migen.genlib.misc import optree @@ -91,7 +89,7 @@ class Decoder(Module): ] # mux (1-hot) slave data return - masked = [Replicate(slave_sel_r[i], len(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)] + masked = [Replicate(slave_sel_r[i], flen(master.dat_r)) & slaves[i][1].dat_r for i in range(ns)] self.comb += master.dat_r.eq(optree("|", masked)) class InterconnectShared(Module): @@ -210,7 +208,7 @@ class SRAM(Module): for i in range(4)] # address and data self.comb += [ - port.adr.eq(self.bus.adr[:len(port.adr)]), + port.adr.eq(self.bus.adr[:flen(port.adr)]), self.bus.dat_r.eq(port.dat_r) ] if not read_only: diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py index 45882078..94f86192 100644 --- a/migen/bus/wishbone2asmi.py +++ b/migen/bus/wishbone2asmi.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.fsm import FSM from migen.genlib.misc import split, displacer, chooser diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py index 5e62de84..5b803787 100644 --- a/migen/bus/wishbone2csr.py +++ b/migen/bus/wishbone2csr.py @@ -1,23 +1,23 @@ +from migen.fhdl.std import * from migen.bus import wishbone from migen.bus import csr -from migen.fhdl.structure import * from migen.genlib.misc import timeline -class WB2CSR: +class WB2CSR(Module): def __init__(self): self.wishbone = wishbone.Interface() self.csr = csr.Interface() - def get_fragment(self): - sync = [ + ### + + self.sync += [ self.csr.we.eq(0), self.csr.dat_w.eq(self.wishbone.dat_w[:csr.data_width]), self.csr.adr.eq(self.wishbone.adr[:14]), self.wishbone.dat_r.eq(self.csr.dat_r) ] - sync += timeline(self.wishbone.cyc & self.wishbone.stb, [ + self.sync += timeline(self.wishbone.cyc & self.wishbone.stb, [ (1, [self.csr.we.eq(self.wishbone.we)]), (2, [self.wishbone.ack.eq(1)]), (3, [self.wishbone.ack.eq(0)]) ]) - return Fragment(sync=sync) diff --git a/migen/fhdl/size.py b/migen/fhdl/size.py new file mode 100644 index 00000000..a1169013 --- /dev/null +++ b/migen/fhdl/size.py @@ -0,0 +1,102 @@ +from migen.fhdl import structure as f + +def log2_int(n, need_pow2=True): + l = 1 + r = 0 + while l < n: + l *= 2 + r += 1 + if need_pow2 and l != n: + raise ValueError("Not a power of 2") + return r + +def bits_for(n, require_sign_bit=False): + if n > 0: + r = log2_int(n + 1, False) + else: + require_sign_bit = True + r = log2_int(-n, False) + if require_sign_bit: + r += 1 + return r + +def value_bits_sign(v): + if isinstance(v, bool): + return 1, False + elif isinstance(v, int): + return bits_for(v), v < 0 + elif isinstance(v, f.Signal): + return v.nbits, v.signed + elif isinstance(v, (f.ClockSignal, f.ResetSignal)): + return 1, False + elif isinstance(v, f._Operator): + obs = list(map(value_bits_sign, v.operands)) + if v.op == "+" or v.op == "-": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return max(obs[0][0], obs[1][0]) + 1, False + elif obs[0][1] and obs[1][1]: + # both operands signed + return max(obs[0][0], obs[1][0]) + 1, True + elif not obs[0][1] and obs[1][1]: + # first operand unsigned (add sign bit), second operand signed + return max(obs[0][0] + 1, obs[1][0]) + 1, True + else: + # first signed, second operand unsigned (add sign bit) + return max(obs[0][0], obs[1][0] + 1) + 1, True + elif v.op == "*": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return obs[0][0] + obs[1][0] + elif obs[0][1] and obs[1][1]: + # both operands signed + return obs[0][0] + obs[1][0] - 1 + else: + # one operand signed, the other unsigned (add sign bit) + return obs[0][0] + obs[1][0] + 1 - 1 + elif v.op == "<<<": + if obs[1][1]: + extra = 2**(obs[1][0] - 1) - 1 + else: + extra = 2**obs[1][0] - 1 + return obs[0][0] + extra, obs[0][1] + elif v.op == ">>>": + if obs[1][1]: + extra = 2**(obs[1][0] - 1) + else: + extra = 0 + return obs[0][0] + extra, obs[0][1] + elif v.op == "&" or v.op == "^" or v.op == "|": + if not obs[0][1] and not obs[1][1]: + # both operands unsigned + return max(obs[0][0], obs[1][0]), False + elif obs[0][1] and obs[1][1]: + # both operands signed + return max(obs[0][0], obs[1][0]), True + elif not obs[0][1] and obs[1][1]: + # first operand unsigned (add sign bit), second operand signed + return max(obs[0][0] + 1, obs[1][0]), True + else: + # first signed, second operand unsigned (add sign bit) + return max(obs[0][0], obs[1][0] + 1), True + elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \ + or v.op == ">" or v.op == ">=": + return 1, False + elif v.op == "~": + return obs[0] + else: + raise TypeError + elif isinstance(v, f._Slice): + return v.stop - v.start, value_bits_sign(v.value)[1] + elif isinstance(v, f.Cat): + return sum(value_bits_sign(sv)[0] for sv in v.l), False + elif isinstance(v, f.Replicate): + return (value_bits_sign(v.v)[0])*v.n, False + elif isinstance(v, f._ArrayProxy): + bsc = map(value_bits_sign, v.choices) + return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc) + else: + raise TypeError + +def flen(v): + return value_bits_sign(v)[0] diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index 59ef7303..f56a7042 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -1,4 +1,5 @@ from migen.fhdl.structure import * +from migen.fhdl.size import bits_for, value_bits_sign from migen.fhdl.tools import * from migen.fhdl.tracer import get_obj_var_name from migen.fhdl.verilog import _printexpr as verilog_printexpr diff --git a/migen/fhdl/std.py b/migen/fhdl/std.py new file mode 100644 index 00000000..ccdc82c0 --- /dev/null +++ b/migen/fhdl/std.py @@ -0,0 +1,4 @@ +from migen.fhdl.structure import * +from migen.fhdl.module import Module +from migen.fhdl.specials import TSTriple, Instance, Memory +from migen.fhdl.size import log2_int, bits_for, flen diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index dea8dc7b..5aee1b3a 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -5,26 +5,6 @@ from collections import defaultdict from migen.fhdl import tracer -def log2_int(n, need_pow2=True): - l = 1 - r = 0 - while l < n: - l *= 2 - r += 1 - if need_pow2 and l != n: - raise ValueError("Not a power of 2") - return r - -def bits_for(n, require_sign_bit=False): - if n > 0: - r = log2_int(n + 1, False) - else: - require_sign_bit = True - r = log2_int(-n, False) - if require_sign_bit: - r += 1 - return r - class HUID: __next_uid = 0 def __init__(self): @@ -88,19 +68,21 @@ class Value(HUID): def __getitem__(self, key): + from migen.fhdl.size import flen + if isinstance(key, int): if key < 0: - key += len(self) + key += flen(self) return _Slice(self, key, key+1) elif isinstance(key, slice): start = key.start or 0 - stop = key.stop or len(self) + stop = key.stop or flen(self) if start < 0: - start += len(self) + start += flen(self) if stop < 0: - stop += len(self) - if stop > len(self): - stop = len(self) + stop += flen(self) + if stop > flen(self): + stop = flen(self) if key.step != None: raise KeyError return _Slice(self, start, stop) @@ -109,9 +91,6 @@ class Value(HUID): def eq(self, r): return _Assign(self, r) - - def __len__(self): - return value_bits_sign(self)[0] def __hash__(self): return HUID.__hash__(self) @@ -142,6 +121,8 @@ class Replicate(Value): class Signal(Value): def __init__(self, bits_sign=None, name=None, variable=False, reset=0, name_override=None, min=None, max=None): + from migen.fhdl.size import bits_for + Value.__init__(self) # determine number of bits and signedness @@ -304,80 +285,3 @@ class Fragment: self.clock_domains + other.clock_domains, self.sim + other.sim) -def value_bits_sign(v): - if isinstance(v, bool): - return 1, False - elif isinstance(v, int): - return bits_for(v), v < 0 - elif isinstance(v, Signal): - return v.nbits, v.signed - elif isinstance(v, (ClockSignal, ResetSignal)): - return 1, False - elif isinstance(v, _Operator): - obs = list(map(value_bits_sign, v.operands)) - if v.op == "+" or v.op == "-": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return max(obs[0][0], obs[1][0]) + 1, False - elif obs[0][1] and obs[1][1]: - # both operands signed - return max(obs[0][0], obs[1][0]) + 1, True - elif not obs[0][1] and obs[1][1]: - # first operand unsigned (add sign bit), second operand signed - return max(obs[0][0] + 1, obs[1][0]) + 1, True - else: - # first signed, second operand unsigned (add sign bit) - return max(obs[0][0], obs[1][0] + 1) + 1, True - elif v.op == "*": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return obs[0][0] + obs[1][0] - elif obs[0][1] and obs[1][1]: - # both operands signed - return obs[0][0] + obs[1][0] - 1 - else: - # one operand signed, the other unsigned (add sign bit) - return obs[0][0] + obs[1][0] + 1 - 1 - elif v.op == "<<<": - if obs[1][1]: - extra = 2**(obs[1][0] - 1) - 1 - else: - extra = 2**obs[1][0] - 1 - return obs[0][0] + extra, obs[0][1] - elif v.op == ">>>": - if obs[1][1]: - extra = 2**(obs[1][0] - 1) - else: - extra = 0 - return obs[0][0] + extra, obs[0][1] - elif v.op == "&" or v.op == "^" or v.op == "|": - if not obs[0][1] and not obs[1][1]: - # both operands unsigned - return max(obs[0][0], obs[1][0]), False - elif obs[0][1] and obs[1][1]: - # both operands signed - return max(obs[0][0], obs[1][0]), True - elif not obs[0][1] and obs[1][1]: - # first operand unsigned (add sign bit), second operand signed - return max(obs[0][0] + 1, obs[1][0]), True - else: - # first signed, second operand unsigned (add sign bit) - return max(obs[0][0], obs[1][0] + 1), True - elif v.op == "<" or v.op == "<=" or v.op == "==" or v.op == "!=" \ - or v.op == ">" or v.op == ">=": - return 1, False - elif v.op == "~": - return obs[0] - else: - raise TypeError - elif isinstance(v, _Slice): - return v.stop - v.start, value_bits_sign(v.value)[1] - elif isinstance(v, Cat): - return sum(value_bits_sign(sv)[0] for sv in v.l), False - elif isinstance(v, Replicate): - return (value_bits_sign(v.v)[0])*v.n, False - elif isinstance(v, _ArrayProxy): - bsc = map(value_bits_sign, v.choices) - return max(bs[0] for bs in bsc), any(bs[1] for bs in bsc) - else: - raise TypeError diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py index fa5e65b3..2d739077 100644 --- a/migen/fhdl/tools.py +++ b/migen/fhdl/tools.py @@ -3,6 +3,7 @@ import collections from migen.fhdl.structure import * from migen.fhdl.structure import _Slice, _Assign from migen.fhdl.visit import NodeVisitor, NodeTransformer +from migen.fhdl.size import value_bits_sign def bitreverse(s): length, signed = value_bits_sign(s) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 6708bdff..66c28799 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -4,6 +4,7 @@ from operator import itemgetter from migen.fhdl.structure import * from migen.fhdl.structure import _Operator, _Slice, _Assign from migen.fhdl.tools import * +from migen.fhdl.size import bits_for, flen from migen.fhdl.namer import Namespace, build_namespace def _printsig(ns, s): @@ -11,8 +12,8 @@ def _printsig(ns, s): n = "signed " else: n = "" - if len(s) > 1: - n += "[" + str(len(s)-1) + ":0] " + if flen(s) > 1: + n += "[" + str(flen(s)-1) + ":0] " n += ns.get_name(s) return n @@ -63,7 +64,7 @@ def _printexpr(ns, node): elif isinstance(node, _Slice): # Verilog does not like us slicing non-array signals... if isinstance(node.value, Signal) \ - and len(node.value) == 1 \ + and flen(node.value) == 1 \ and node.start == 0 and node.stop == 1: return _printexpr(ns, node.value) diff --git a/migen/flow/actor.py b/migen/flow/actor.py index 6d05917f..d3f4ec17 100644 --- a/migen/flow/actor.py +++ b/migen/flow/actor.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.misc import optree from migen.genlib.record import * diff --git a/migen/flow/hooks.py b/migen/flow/hooks.py index 7c20a0eb..2c505558 100644 --- a/migen/flow/hooks.py +++ b/migen/flow/hooks.py @@ -1,7 +1,6 @@ from collections import defaultdict -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * class EndpointSimHook(Module): diff --git a/migen/flow/isd.py b/migen/flow/isd.py index 1b7d2ea3..8238f5e1 100644 --- a/migen/flow/isd.py +++ b/migen/flow/isd.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.bank.description import * from migen.flow.hooks import DFGHook diff --git a/migen/flow/network.py b/migen/flow/network.py index deaacd32..9bf775a7 100644 --- a/migen/flow/network.py +++ b/migen/flow/network.py @@ -1,6 +1,6 @@ from networkx import MultiDiGraph -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.genlib.misc import optree from migen.flow.actor import * from migen.flow import plumbing diff --git a/migen/flow/plumbing.py b/migen/flow/plumbing.py index 8edec896..23301631 100644 --- a/migen/flow/plumbing.py +++ b/migen/flow/plumbing.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.flow.actor import * from migen.genlib.record import * from migen.genlib.misc import optree diff --git a/migen/genlib/buffers.py b/migen/genlib/buffers.py index 29cee986..34a9a913 100644 --- a/migen/genlib/buffers.py +++ b/migen/genlib/buffers.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * class ReorderSlot: def __init__(self, tag_width, data_width): diff --git a/migen/genlib/cdc.py b/migen/genlib/cdc.py index f194ecb7..5759c929 100644 --- a/migen/genlib/cdc.py +++ b/migen/genlib/cdc.py @@ -1,5 +1,5 @@ -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * +from migen.fhdl.size import value_bits_sign from migen.fhdl.specials import Special from migen.fhdl.tools import list_signals diff --git a/migen/genlib/complex.py b/migen/genlib/complex.py index 34c98224..e876fb63 100644 --- a/migen/genlib/complex.py +++ b/migen/genlib/complex.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * class Complex: def __init__(self, real, imag): diff --git a/migen/genlib/divider.py b/migen/genlib/divider.py index 62b87c21..05459332 100644 --- a/migen/genlib/divider.py +++ b/migen/genlib/divider.py @@ -1,9 +1,7 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * -class Divider: +class Divider(Module): def __init__(self, w): - self.w = w - self.start_i = Signal() self.dividend_i = Signal(w) self.divisor_i = Signal(w) @@ -11,21 +9,20 @@ class Divider: self.quotient_o = Signal(w) self.remainder_o = Signal(w) - def get_fragment(self): - w = self.w + ### qr = Signal(2*w) counter = Signal(max=w+1) divisor_r = Signal(w) diff = Signal(w+1) - comb = [ + self.comb += [ self.quotient_o.eq(qr[:w]), self.remainder_o.eq(qr[w:]), self.ready_o.eq(counter == 0), diff.eq(self.remainder_o - divisor_r) ] - sync = [ + self.sync += [ If(self.start_i, counter.eq(w), qr.eq(self.dividend_i), @@ -39,4 +36,3 @@ class Divider: counter.eq(counter - 1) ) ] - return Fragment(comb, sync) diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py index c0e1e107..6c4a4962 100644 --- a/migen/genlib/fifo.py +++ b/migen/genlib/fifo.py @@ -1,10 +1,8 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter def _inc(signal, modulo): - if modulo == 2**len(signal): + if modulo == 2**flen(signal): return signal.eq(signal + 1) else: return If(signal == (modulo - 1), diff --git a/migen/genlib/fsm.py b/migen/genlib/fsm.py index 85f3a401..300e8e9f 100644 --- a/migen/genlib/fsm.py +++ b/migen/genlib/fsm.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * class FSM: def __init__(self, *states, delayed_enters=[]): diff --git a/migen/genlib/ioo.py b/migen/genlib/ioo.py index 20947d6a..66d411b0 100644 --- a/migen/genlib/ioo.py +++ b/migen/genlib/ioo.py @@ -1,5 +1,4 @@ -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.actor import _Endpoint from migen.flow.transactions import * diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py index fc0469db..97d0be0e 100644 --- a/migen/genlib/misc.py +++ b/migen/genlib/misc.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.fhdl.structure import _Operator def optree(op, operands, lb=None, ub=None, default=None): @@ -30,8 +30,8 @@ def split(v, *counts): def displacer(signal, shift, output, n=None, reverse=False): if n is None: - n = 2**len(shift) - w = len(signal) + n = 2**flen(shift) + w = flen(signal) if reverse: r = reversed(range(n)) else: @@ -41,8 +41,8 @@ def displacer(signal, shift, output, n=None, reverse=False): def chooser(signal, shift, output, n=None, reverse=False): if n is None: - n = 2**len(shift) - w = len(output) + n = 2**flen(shift) + w = flen(output) cases = {} for i in range(n): if reverse: diff --git a/migen/genlib/record.py b/migen/genlib/record.py index 13b730fb..d2d355ce 100644 --- a/migen/genlib/record.py +++ b/migen/genlib/record.py @@ -1,4 +1,4 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.fhdl.tracer import get_obj_var_name from migen.genlib.misc import optree diff --git a/migen/genlib/roundrobin.py b/migen/genlib/roundrobin.py index f55b3fee..15bec5c7 100644 --- a/migen/genlib/roundrobin.py +++ b/migen/genlib/roundrobin.py @@ -1,23 +1,23 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * (SP_WITHDRAW, SP_CE) = range(2) -class RoundRobin: +class RoundRobin(Module): def __init__(self, n, switch_policy=SP_WITHDRAW): - self.n = n - self.request = Signal(self.n) - self.grant = Signal(max=self.n) + self.request = Signal(n) + self.grant = Signal(max=n) self.switch_policy = switch_policy if self.switch_policy == SP_CE: self.ce = Signal() - def get_fragment(self): - if self.n > 1: + ### + + if n > 1: cases = {} - for i in range(self.n): + for i in range(n): switch = [] - for j in reversed(range(i+1,i+self.n)): - t = j % self.n + for j in reversed(range(i+1,i+n)): + t = j % n switch = [ If(self.request[t], self.grant.eq(t) @@ -33,6 +33,6 @@ class RoundRobin: statement = Case(self.grant, cases) if self.switch_policy == SP_CE: statement = If(self.ce, statement) - return Fragment(sync=[statement]) + self.sync += statement else: - return Fragment([self.grant.eq(0)]) + self.comb += self.grant.eq(0) diff --git a/migen/pytholite/io.py b/migen/pytholite/io.py index 6b6cbcb2..cda649e9 100644 --- a/migen/pytholite/io.py +++ b/migen/pytholite/io.py @@ -1,8 +1,7 @@ import ast from itertools import zip_longest -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.flow.actor import Source, Sink from migen.flow.transactions import * from migen.bus import wishbone diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py index 175aa17e..5e05e5be 100644 --- a/migen/pytholite/reg.py +++ b/migen/pytholite/reg.py @@ -1,7 +1,6 @@ from operator import itemgetter -from migen.fhdl.structure import * -from migen.fhdl.module import Module +from migen.fhdl.std import * from migen.fhdl import visit as fhdl class AbstractLoad: diff --git a/migen/sim/generic.py b/migen/sim/generic.py index 960c15bb..ab52e29e 100644 --- a/migen/sim/generic.py +++ b/migen/sim/generic.py @@ -1,8 +1,4 @@ -# Copyright (C) 2012 Vermeer Manufacturing Co. -# License: GPLv3 with additional permissions (see README). - -from migen.fhdl.structure import * -from migen.fhdl.specials import Memory +from migen.fhdl.std import * from migen.fhdl import verilog from migen.sim.ipc import * from migen.sim import icarus @@ -132,7 +128,7 @@ class Simulator: nbits = item.width else: signed = item.signed - nbits = len(item) + nbits = flen(item) value = reply.value & (2**nbits - 1) if signed and (value & 2**(nbits - 1)): value -= 2**nbits @@ -145,7 +141,7 @@ class Simulator: if isinstance(item, Memory): nbits = item.width else: - nbits = len(item) + nbits = flen(item) if value < 0: value += 2**nbits assert(value >= 0 and value < 2**nbits)