From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 23:10:11 +0000 (-0700)
Subject: verilog: attributes before task enable (but 13 s/r conflicts)
X-Git-Tag: working-ls180~544^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7101ef550ba4b215d41fc82e52e3aa714afcbdbe;p=yosys.git

verilog: attributes before task enable (but 13 s/r conflicts)
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index db9a130cf..fd4ff68a9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2217,23 +2217,23 @@ behavioral_stmt:
 	defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
 	non_opt_delay behavioral_stmt |
 	simple_behavioral_stmt ';' | ';' |
-	hierarchical_id attr {
+	attr hierarchical_id {
 		AstNode *node = new AstNode(AST_TCALL);
-		node->str = *$1;
-		delete $1;
+		node->str = *$2;
+		delete $2;
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-		append_attr(node, $2);
+		append_attr(node, $1);
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
-	TOK_MSG_TASKS attr {
+	attr TOK_MSG_TASKS {
 		AstNode *node = new AstNode(AST_TCALL);
-		node->str = *$1;
-		delete $1;
+		node->str = *$2;
+		delete $2;
 		ast_stack.back()->children.push_back(node);
 		ast_stack.push_back(node);
-		append_attr(node, $2);
+		append_attr(node, $1);
 	} opt_arg_list ';'{
 		ast_stack.pop_back();
 	} |
@@ -2330,8 +2330,6 @@ behavioral_stmt:
 		ast_stack.pop_back();
 	};
 
-	;
-
 unique_case_attr:
 	/* empty */ {
 		$$ = false;