From: Roland Scheidegger Date: Mon, 26 Oct 2015 15:44:47 +0000 (+0100) Subject: gallivm: disable f16c when not using AVX X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=711489648bcce5cd8fcf14e73e5affe069010c01;p=mesa.git gallivm: disable f16c when not using AVX f16c intrinsic can only be emitted when AVX is used. So when we disable AVX due to forcing 128bit vectors we must not use this intrinsic (depending on llvm version, this worked previously because llvm used AVX even when we didn't tell it to, however I've seen this fail with llvm 3.3 since 718249843b915decf8fccec92e466ac1a6219934 which seems to have the side effect of disabling avx in llvm albeit it only touches sse flags really, but with ea421e919ae6e72e1319fb205c42a6fb53ca2f82 it's now really disabled). Albeit being able to use AVX with 128bit vectors also would have its uses, the code as is really was meant to emulate jit code creation for less capable cpus. v2: add some (ifdefed out) missing de-featuring options for simulating less capable cpus. Reviewed-by: Nicolai Hähnle Reviewed-by: Jose Fonseca --- diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c index 017d0752060..96aba7370c1 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_init.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c @@ -427,6 +427,7 @@ lp_build_init(void) */ util_cpu_caps.has_avx = 0; util_cpu_caps.has_avx2 = 0; + util_cpu_caps.has_f16c = 0; } #ifdef PIPE_ARCH_PPC_64 @@ -458,7 +459,9 @@ lp_build_init(void) util_cpu_caps.has_sse3 = 0; util_cpu_caps.has_ssse3 = 0; util_cpu_caps.has_sse4_1 = 0; + util_cpu_caps.has_sse4_2 = 0; util_cpu_caps.has_avx = 0; + util_cpu_caps.has_avx2 = 0; util_cpu_caps.has_f16c = 0; #endif