From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 30 Jul 2018 10:00:55 +0000 (+0100)
Subject: sort out jtag clock/reset interchange
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=711da41d5e3520e617220484b3e9e99ab8298489;p=pinmux.git

sort out jtag clock/reset interchange
---

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 397c1c0..1892fc1 100644
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -253,10 +253,10 @@ else"""
         if ck == PBase.get_clock_reset(self, name, count):
             return ''
         if ctype == 'slow':
-            spc = "sp_clock, sp_reset"
+            spc = self.get_clk_spc(ctype)
         else:
             spc = ck
-            ck = "core_clock, core_reset"
+            ck = self.get_clk_spc(ctype)
         template = """\
 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             {2}, {3});"""
@@ -285,15 +285,21 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                 ret.append(template.format("Bit#(1)", n_, spc, ck))
         return '\n'.join(ret)
 
+    def get_clk_spc(self, ctype):
+        if ctype == 'slow':
+            return "sp_clock, sp_reset"
+        else:
+            return "core_clock, core_reset"
+
     def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
         ck = self.get_clock_reset(name, count)
         if ck == PBase.get_clock_reset(self, name, count):
             return ''
         if ctype == 'slow':
-            spc = "sp_clock, sp_reset"
+            spc = self.get_clk_spc(ctype)
         else:
             spc = ck
-            ck = "core_clock, core_reset"
+            ck = self.get_clk_spc(ctype)
         template = """\
 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             {2}, {3});"""
diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index c0891fd..c62b009 100644
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -13,9 +13,12 @@ class jtag(PBase):
         # YUK!
         return "interface Ifc_jtagdtm jtag{0}_out;".format(count)
 
-    def get_clock_reset(self, name, count):
+    def get_clk_spc(self, typ):
         return "tck, trst"
 
+    def get_clock_reset(self, name, count):
+        return "slow_clock,  slow_reset"
+
     def pinname_in(self, pname):
         return {'tms': 'tms',
                 'tdi': 'tdi',