From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Fri, 22 Nov 2019 07:59:54 +0000 (+0100)
Subject: [ARC] Fix ARC target specific tests.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=713877cbd73783fac1a1013cefd24cc273bb4635;p=gcc.git

[ARC] Fix ARC target specific tests.

Fix ARC specific tests by improving the matching pattern and adding
the missing functionality in arc.exp

gcc/tests
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
	output assembly.
	* gcc.target/arc/arc.exp (check_effective_target_codedensity):
	Add.
	* gcc.target/arc/cmem-7.c: Fix matching patterns.
	* gcc.target/arc/cmem-bit-1.c: Likewise.
	* gcc.target/arc/cmem-bit-2.c: Likewise.
	* gcc.target/arc/cmem-bit-3.c: Likewise.
	* gcc.target/arc/cmem-bit-4.c: Likewise.
	* gcc.target/arc/interrupt-2.c: Match rtie insn for A7.
	* gcc.target/arc/store-merge-1.c: This test is only meaningful for
	architectures with double load/store operations.

From-SVN: r278609
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 38ff666a493..181e478bf90 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,18 @@
+2019-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/add_n-combine.c: Match add1/2/3 instruction in
+	output assembly.
+	* gcc.target/arc/arc.exp (check_effective_target_codedensity):
+	Add.
+	* gcc.target/arc/cmem-7.c: Fix matching patterns.
+	* gcc.target/arc/cmem-bit-1.c: Likewise.
+	* gcc.target/arc/cmem-bit-2.c: Likewise.
+	* gcc.target/arc/cmem-bit-3.c: Likewise.
+	* gcc.target/arc/cmem-bit-4.c: Likewise.
+	* gcc.target/arc/interrupt-2.c: Match rtie insn for A7.
+	* gcc.target/arc/store-merge-1.c: This test is only meaningful for
+	architectures with double load/store operations.
+
 2019-11-21  Martin Sebor  <msebor@redhat.com>
 
 	* gcc.dg/strlenopt-66.c: Avoid buffer overflow.  Add more test cases.
diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c
index cd32ed386f5..bc400df669e 100644
--- a/gcc/testsuite/gcc.target/arc/add_n-combine.c
+++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c
@@ -1,5 +1,5 @@
 /* { dg-do compile }  */
-/* { dg-options "-O2 -fdump-rtl-combine" }  */
+/* { dg-options "-O2" }  */
 
 struct b1 {
       char c;
@@ -45,4 +45,6 @@ void f() {
   a(at3.bn[bu]);
 }
 
-/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */
+/* { dg-final { scan-assembler "add1" } } */
+/* { dg-final { scan-assembler "add2" } } */
+/* { dg-final { scan-assembler "add3" } } */
diff --git a/gcc/testsuite/gcc.target/arc/arc.exp b/gcc/testsuite/gcc.target/arc/arc.exp
index 55e12137a2a..ac1d5b67048 100644
--- a/gcc/testsuite/gcc.target/arc/arc.exp
+++ b/gcc/testsuite/gcc.target/arc/arc.exp
@@ -94,6 +94,16 @@ proc check_effective_target_barrelshifter { } {
     }]
 }
 
+#return 1 if we have code density option on.
+proc check_effective_target_codedensity { } {
+    return [check_no_compiler_messages codedensity assembly {
+        #if !defined(__ARC_CODE_DENSITY__)
+        #error No code density option for this config
+        #endif
+    }]
+}
+
+
 #return 1 if we use ARCv2 Accumulator registers
 proc check_effective_target_accregs { } {
     return [check_no_compiler_messages accregs assembly {
diff --git a/gcc/testsuite/gcc.target/arc/cmem-7.c b/gcc/testsuite/gcc.target/arc/cmem-7.c
index 02673271172..ad7f25d9f8c 100644
--- a/gcc/testsuite/gcc.target/arc/cmem-7.c
+++ b/gcc/testsuite/gcc.target/arc/cmem-7.c
@@ -21,7 +21,7 @@ some_function ()
   return 0;
 }
 
-/* { dg-final { scan-assembler "xldb \[^\n\]*@ss" } } */
-/* { dg-final { scan-assembler "xstb \[^\n\]*@ss" } } */
-/* { dg-final { scan-assembler-not "xldb \[^\n\]*@tt" } } */
-/* { dg-final { scan-assembler-not "xstb \[^\n\]*@tt" } } */
+/* { dg-final { scan-assembler "xldb\\s+\[^\n\]*@ss" } } */
+/* { dg-final { scan-assembler "xstb\\s+\[^\n\]*@ss" } } */
+/* { dg-final { scan-assembler-not "xldb\\s+\[^\n\]*@tt" } } */
+/* { dg-final { scan-assembler-not "xstb\\s+\[^\n\]*@tt" } } */
diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-1.c b/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
index d49ab5cd44f..d3471a2e621 100644
--- a/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
+++ b/gcc/testsuite/gcc.target/arc/cmem-bit-1.c
@@ -16,5 +16,5 @@ void foo() {
     bar();
 }
 
-/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
-/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */
+/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
+/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-2.c b/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
index 45b49c6dfc3..4b022944f60 100644
--- a/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
+++ b/gcc/testsuite/gcc.target/arc/cmem-bit-2.c
@@ -16,5 +16,5 @@ void foo() {
     bar();
 }
 
-/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
-/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */
+/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
+/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-3.c b/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
index 371ff2bca8b..40fbb934bf9 100644
--- a/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
+++ b/gcc/testsuite/gcc.target/arc/cmem-bit-3.c
@@ -16,5 +16,5 @@ void foo() {
     bar();
 }
 
-/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
-/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */
+/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
+/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/cmem-bit-4.c b/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
index a95c6ae14d3..288a6a03583 100644
--- a/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
+++ b/gcc/testsuite/gcc.target/arc/cmem-bit-4.c
@@ -16,5 +16,5 @@ void foo() {
     bar();
 }
 
-/* { dg-final { scan-assembler "xldb r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
-/* { dg-final { scan-assembler "btst_s r\[0-9\]+,7" { target arceb-*-* } } } */
+/* { dg-final { scan-assembler "xldb\\s+r\[0-9\]+,\\\[@a_strange_bool\\\]" } } */
+/* { dg-final { scan-assembler "btst_s\\s+r\[0-9\]+,7" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/interrupt-2.c b/gcc/testsuite/gcc.target/arc/interrupt-2.c
index 285ebd57a22..09c6f4d216e 100644
--- a/gcc/testsuite/gcc.target/arc/interrupt-2.c
+++ b/gcc/testsuite/gcc.target/arc/interrupt-2.c
@@ -3,4 +3,5 @@ void __attribute__ ((interrupt("ilink2")))
 handler1 (void)
 {
 }
-/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 } } */
+/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 { target { arc6xx } } } } */
+/* { dg-final { scan-assembler-times "rtie" 1 { target { arc700 } } } } */
diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c
index e9d4e57c27d..a133e8719b4 100644
--- a/gcc/testsuite/gcc.target/arc/store-merge-1.c
+++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
-/* { dg-options "-O3" } */
+/* { dg-require-effective-target archs }*/
+/* { dg-options "-O3 -mll64" } */
 
 /* This tests checks if we use st w6,[reg] format.  */