From: Matt Turner Date: Tue, 21 Jan 2020 18:44:59 +0000 (-0800) Subject: intel/compiler: Don't disassemble align1 3-src operands on Gen < 10 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=713c123bfa90fa845cf603a2d82a338b363cb4ee;p=mesa.git intel/compiler: Don't disassemble align1 3-src operands on Gen < 10 Since the platforms don't support align1 3-src instructions, the contents of these operands are not going to be meaningful. Just don't print them to avoid hitting some assertions in brw_inst functions. Reviewed-by: Caio Marcelo de Oliveira Filho Part-of: --- diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 31d932b9cba..e3e9b509f1b 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -829,6 +829,9 @@ dest_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins unsigned subreg_nr; enum brw_reg_type type; + if (devinfo->gen < 10 && is_align1) + return 0; + if (devinfo->gen == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst)) reg_file = BRW_MESSAGE_REGISTER_FILE; else if (devinfo->gen >= 12) @@ -1101,6 +1104,9 @@ src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins bool is_scalar_region; bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + if (devinfo->gen < 10 && is_align1) + return 0; + if (is_align1) { if (devinfo->gen >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) { _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst); @@ -1184,6 +1190,9 @@ src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins bool is_scalar_region; bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + if (devinfo->gen < 10 && is_align1) + return 0; + if (is_align1) { if (devinfo->gen >= 12) { _file = brw_inst_3src_a1_src1_reg_file(devinfo, inst); @@ -1254,6 +1263,9 @@ src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins bool is_scalar_region; bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1; + if (devinfo->gen < 10 && is_align1) + return 0; + if (is_align1) { if (devinfo->gen >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) { _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);