From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Sun, 29 Aug 2021 19:44:52 +0000 (+0000)
Subject: fixedarith: switch divdeX to XLEN
X-Git-Tag: xlen-bcd~53
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=713d8336c0056d1085a3cecfeee3675befd59e13;p=openpower-isa.git

fixedarith: switch divdeX to XLEN
---

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index a23b4023..5832be51 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -720,22 +720,22 @@ XO-Form
 
 Pseudo-code:
 
-    dividend[0:127] <- (RA) || [0]*64
-    divisor[0:127] <- EXTS128((RB))
-    if (((dividend = 0x8000_0000_0000_0000_0000_0000_0000_0000) &
-         (divisor = [1]*128)) |
-         (divisor = [0]*128)) then
+    dividend[0:(XLEN*2)-1] <- (RA) || [0]*XLEN
+    divisor[0:(XLEN*2)-1] <- EXTS128((RB))
+    if (((dividend = (0b1 || ([0b0] * ((XLEN*2)-1)))) &
+         (divisor = [1]*(XLEN*2))) |
+         (divisor = [0]*(XLEN*2))) then
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        result64[0:127] <- EXTS128(result[64:127])
-        if (result64 = result) then
-            RT <- result[64:127]
+        result_half[0:(XLEN*2)-1] <- EXTS128(result[XLEN:(XLEN*2)-1])
+        if (result_half = result) then
+            RT <- result[XLEN:(XLEN*2)-1]
             overflow <- 0
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undefined([0]*64)
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
 
 Special Registers Altered: