From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Sun, 21 Sep 2014 17:56:25 +0000 (+0200)
Subject: predicates.md (ca_operand): Allow subregs.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=714355645971432ccd9523fcf3ffa2eb3e7cd610;p=gcc.git

predicates.md (ca_operand): Allow subregs.

2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/predicates.md (ca_operand): Allow subregs.
	(input_operand): Do not allow ca_operand.
	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): For the
	carry bit, allow SImode and Pmode.
	(rs6000_init_hard_regno_mode_ok): Make the carry bit class NO_REGS.

From-SVN: r215429
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b60797c0775..26643bc7c8a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-09-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/predicates.md (ca_operand): Allow subregs.
+	(input_operand): Do not allow ca_operand.
+	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): For the
+	carry bit, allow SImode and Pmode.
+	(rs6000_init_hard_regno_mode_ok): Make the carry bit class NO_REGS.
+
 2014-09-21  Uros Bizjak  <ubizjak@gmail.com>
 
 	* config/i386/i386.c (ix86_expand_call): Generate MS->SYSV extra
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 379e0a25dbf..ae6e3ed6064 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -116,8 +116,16 @@
 
 ;; Return 1 if op is the carry register.
 (define_predicate "ca_operand"
-  (and (match_code "reg")
-       (match_test "CA_REGNO_P (REGNO (op))")))
+  (match_operand 0 "register_operand")
+{
+  if (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+
+  if (!REG_P (op))
+    return 0;
+
+  return CA_REGNO_P (REGNO (op));
+})
 
 ;; Return 1 if op is a signed 5-bit constant integer.
 (define_predicate "s5bit_cint_operand"
@@ -1121,6 +1129,10 @@
       || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
     return register_operand (op, mode);
 
+  /* We don't allow moving the carry bit around.  */
+  if (ca_operand (op, mode))
+    return 0;
+
   /* The only cases left are integral modes one word or smaller (we
      do not get called for MODE_CC values).  These can be in any
      register.  */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ffff264507d..62001b01a56 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1780,7 +1780,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
     return GET_MODE_CLASS (mode) == MODE_CC;
 
   if (CA_REGNO_P (regno))
-    return mode == BImode;
+    return mode == Pmode || mode == SImode;
 
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))
@@ -2475,7 +2475,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
   rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
   rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
-  rs6000_regno_regclass[CA_REGNO] = CA_REGS;
+  rs6000_regno_regclass[CA_REGNO] = NO_REGS;
   rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
   rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;