From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Apr 2020 00:03:28 +0000 (-0700)
Subject: timinginfo: ignore $specify2 cells if EN is false
X-Git-Tag: working-ls180~549^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7146c0339e0b79ec24bc89e7fdf15331436e0e53;p=yosys.git

timinginfo: ignore $specify2 cells if EN is false
---

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 36908868c..d818e580b 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -82,6 +82,9 @@ struct TimingInfo
 
 		for (auto cell : module->cells()) {
 			if (cell->type == ID($specify2)) {
+				auto en = cell->getPort(ID::EN);
+				if (en.is_fully_const() && !en.as_bool())
+					continue;
 				auto src = cell->getPort(ID::SRC);
 				auto dst = cell->getPort(ID::DST);
 				for (const auto &c : src.chunks())