From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Mon, 8 Apr 2013 18:28:11 +0000 (+0200)
Subject: crg: apply constraint to IO pins, not internal signals
X-Git-Tag: 24jan2021_ls180~2099^2~443^2~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=715d332c3d76b89053e15259accc4c4ae979e51b;p=litex.git

crg: apply constraint to IO pins, not internal signals
---

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 7d967742..83ae9c4e 100644
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -3,9 +3,11 @@ from migen.fhdl.module import Module
 
 class SimpleCRG(Module):
 	def __init__(self, platform, clk_name, rst_name, rst_invert=False):
+			self._clk = platform.request(clk_name)
+			self._rst = platform.request(rst_name)
 			self.clock_domains.cd_sys = ClockDomain()
-			self.comb += self.cd_sys.clk.eq(platform.request(clk_name))
+			self.comb += self.cd_sys.clk.eq(self._clk)
 			if rst_invert:
-				self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
+				self.comb += self.cd_sys.rst.eq(~self._rst)
 			else:
-				self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
+				self.comb += self.cd_sys.rst.eq(self._rst)
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 6a1e9d7e..a6c31c00 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
 class CRG_SE(SimpleCRG):
 	def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
 		SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
-		_add_period_constraint(platform, self.cd_sys.clk, period)
+		_add_period_constraint(platform, self._clk, period)
 
 class CRG_DS(Module):
 	def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):