From: lkcl Date: Thu, 8 Sep 2022 16:40:26 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~605 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=71608102b1636800e6903921fc7da4016421b6ee;p=libreriscv.git --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index c5fda8820..cd106f017 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -21,7 +21,10 @@ Links This proposal is to extend the Power ISA with an Abstract RISC-Paradigm Vectorisation Concept that may be applied to **all and any** suitable Scalar instructions, present and future, in the Scalar Power ISA. -**It is not a Traditional Vector ISA and therefore does not add Vector opcodes of any kind**. +The Vectorisation System is called "Simple-V" and the Prefix Format +is called "SVP64". + +**Simple-V is not a Traditional Vector ISA and therefore does not add Vector opcodes of any kind**. An ISA Concept similar to Simple-V was originally invented in 1994 by Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not have an @@ -59,6 +62,7 @@ Simple-V has been subdivided into levels akin to the Power ISA Compliancy Levels For now Let us call them "SV Compliancy Levels" to distinguish the two. The reason for the SV Compliancy Levels is the same as for the Power ISA Compliancy Levels (SFFS, SFS): to not overburden implementors with features that they do not need. + *There is no dependence between the two types of Compliancy Levels* The resources below therefore are not all required for all SV Compliancy Levels but